Provided by: libverilog-perl_3.460-1_amd64 bug


       Verilog::EditFiles - Split Verilog modules into separate files.


       See splitmodule command.

          use Verilog::EditFiles;
          my $split = Verilog::EditFiles->new
              (outdir => "processed_rtl",
               translate_synthesis => 0,
               lint_header => undef,
               celldefine => 1,
          $split->edit_file(filename=>"foo", cb => sub { return $_[0]; });


       Verilog::EditFiles provides a easy way to split library Verilog files that contain
       multiple modules into many files with one module per file.


       new (...)
           Create a new Verilog::EditFiles object.  Named parameters may be specified:

               If true, add "`celldefine" before every module statement.

               For the write_lint method, the name of the linter to use.  Defaults to "vlint

               If defined, add the provided text before every module statement.  Generally used
               to insert lint off pragmas.

               Name of the directory to write the output modules to.  Defaults to ".".

               Name of the program to add to comments.  Defaults to "Verilog::EditFiles".

               If defined, add the provided text before every module statement.  Generally set to
               the next needed to #include a timescale file.  Use with timescale_removal.

               If set, remove any `timescales.

               If 1, replace any synopsys translate on/offs with "`ifdef SYNTHESIS" and
               "`endif"s.  If set to a string, use that string instead of "SYNTHESIS".

               The suffix to add to convert a module name into a filename.  Defaults to ".v".

               If true, print what files are being read and written.

           Read from the specified filenames.

           If there is no module statement in the file, assume it is a include file, and when
           write_files is called, place all of the file contents into the output.  If there is a
           module statement, when write_files is called place all following output into a file
           named based on the module, with .v added.

           Write all of the files created by read_and_split to the outdir.

           Create a shell script that will lint every file created by write_files.  If a
           "filename" parameter is not provided, "" will be written in the default

       $self->edit_file(filename=>..., cb=>sub{...})
           Read a file, edit it with the provided callback, and save it if it has changed.  The
           "filename" parameter is the filename to read.  The "write_filename" parameter is the
           filename to write, defaulting to the same name as the filename to read.  The "cb"
           parameter is a reference to a callback which takes the string of file contents and
           returns the string to write back.  Often the callback will simply perform a search and


       Verilog-Perl is part of the <> free Verilog EDA software tool
       suite.  The latest version is available from CPAN and from

       Copyright 2006-2019 by Wilson Snyder.  This package is free software; you can redistribute
       it and/or modify it under the terms of either the GNU Lesser General Public License
       Version 3 or the Perl Artistic License Version 2.0.


       Wilson Snyder <>