Provided by: libverilog-perl_3.460-1_amd64 bug


       Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist


         use Verilog::Netlist;

         my $cell = $module->find_cell('cellname');
         print $cell->name;


       A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in
       the current module.


       See also Verilog::Netlist::Subclass for additional accessors and methods.

           Returns any comments following the definition.  keep_comments=>1 must be passed to
           Verilog::Netlist::new for comments to be retained.

           Delete the cell from the module it's under.

           True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.

           Pointer to the module the cell is in.

           The instantiation name of the cell.

           Reference to the Verilog::Netlist the cell is under.

           List of Verilog::Netlist::Pin connections for the cell.

           List of name sorted Verilog::Netlist::Pin connections for the cell.

           The range for the cell (e.g. "[1:0]") or undef if not ranged.

           Reference to the Verilog::Netlist::Module the cell instantiates.  Only valid after the
           design is linked.

           The module name the cell instantiates (under the cell).


       See also Verilog::Netlist::Subclass for additional accessors and methods.

           Checks the cell for errors.  Normally called by Verilog::Netlist::lint.

           Creates a new Verilog::Netlist::Pin connection for this cell.

           Returns all Verilog::Netlist::Pin connections for this cell.

           Prints debugging information for this cell.


       Verilog-Perl is part of the <> free Verilog EDA software tool
       suite.  The latest version is available from CPAN and from

       Copyright 2000-2019 by Wilson Snyder.  This package is free software; you can redistribute
       it and/or modify it under the terms of either the GNU Lesser General Public License
       Version 3 or the Perl Artistic License Version 2.0.


       Wilson Snyder <>


       Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist