Provided by: libverilog-perl_3.460-1_amd64
Verilog::Netlist::Port - Port for a Verilog Module
use Verilog::Netlist; ... my $port = $module->find_port('pinname'); print $port->name;
A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->array Any array declaration for the port. This only applies to Verilog 1995 style ports which can declare port bits independently from the signal declarations. When using Verilog 2001 style ports, see the matching net declaration's data_type, msb and lsb methods instead, for example "$module-"find_net($port->name)->data_type>. $self->comment Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. $self->data_type The SystemVerilog data type of the port. $self->direction The direction of the port: "in", "out", or "inout". $self->module Reference to the Verilog::Netlist::Module the port is in. $self->name The name of the port. $self->net Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked. $self->type Approximately an alias of data_type for backward compatibility. Do not use for new applications.
See also Verilog::Netlist::Subclass for additional accessors and methods. $self->dump Prints debugging information for this port.
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <http://www.veripool.org/verilog-perl>. Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <email@example.com>
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist