Provided by: libbcm2835-dev_1.73+ds-1_amd64 bug

NAME

       constants - Constants for passing to and from library functions

SYNOPSIS

   Macros
       #define HIGH   0x1
       #define LOW   0x0
       #define MIN(a,  b)   (a < b ? a : b)
       #define BCM2835_CORE_CLK_HZ   250000000
       #define BMC2835_RPI2_DT_FILENAME   '/proc/device-tree/soc/ranges'
       #define BCM2835_PERI_BASE   0x20000000
       #define BCM2835_PERI_SIZE   0x01000000
       #define BCM2835_RPI2_PERI_BASE   0x3F000000
       #define BCM2835_RPI4_PERI_BASE   0xFE000000
       #define BCM2835_RPI4_PERI_SIZE   0x01800000
       #define BCM2835_ST_BASE   0x3000
       #define BCM2835_GPIO_PADS   0x100000
       #define BCM2835_CLOCK_BASE   0x101000
       #define BCM2835_GPIO_BASE   0x200000
       #define BCM2835_SPI0_BASE   0x204000
       #define BCM2835_BSC0_BASE   0x205000
       #define BCM2835_GPIO_PWM   0x20C000
       #define BCM2835_AUX_BASE   0x215000
       #define BCM2835_SPI1_BASE   0x215080
       #define BCM2835_SPI2_BASE   0x2150C0
       #define BCM2835_BSC1_BASE   0x804000
       #define BCM2835_SMI_BASE   0x600000
       #define BCM2835_PAGE_SIZE   (4*1024)
       #define BCM2835_BLOCK_SIZE   (4*1024)
       #define BCM2835_GPFSEL0   0x0000
       #define BCM2835_GPFSEL1   0x0004
       #define BCM2835_GPFSEL2   0x0008
       #define BCM2835_GPFSEL3   0x000c
       #define BCM2835_GPFSEL4   0x0010
       #define BCM2835_GPFSEL5   0x0014
       #define BCM2835_GPSET0   0x001c
       #define BCM2835_GPSET1   0x0020
       #define BCM2835_GPCLR0   0x0028
       #define BCM2835_GPCLR1   0x002c
       #define BCM2835_GPLEV0   0x0034
       #define BCM2835_GPLEV1   0x0038
       #define BCM2835_GPEDS0   0x0040
       #define BCM2835_GPEDS1   0x0044
       #define BCM2835_GPREN0   0x004c
       #define BCM2835_GPREN1   0x0050
       #define BCM2835_GPFEN0   0x0058
       #define BCM2835_GPFEN1   0x005c
       #define BCM2835_GPHEN0   0x0064
       #define BCM2835_GPHEN1   0x0068
       #define BCM2835_GPLEN0   0x0070
       #define BCM2835_GPLEN1   0x0074
       #define BCM2835_GPAREN0   0x007c
       #define BCM2835_GPAREN1   0x0080
       #define BCM2835_GPAFEN0   0x0088
       #define BCM2835_GPAFEN1   0x008c
       #define BCM2835_GPPUD   0x0094
       #define BCM2835_GPPUDCLK0   0x0098
       #define BCM2835_GPPUDCLK1   0x009c
       #define BCM2835_GPPUPPDN0   0x00e4 /* Pin pull-up/down for pins 15:0  */
       #define BCM2835_GPPUPPDN1   0x00e8 /* Pin pull-up/down for pins 31:16 */
       #define BCM2835_GPPUPPDN2   0x00ec /* Pin pull-up/down for pins 47:32 */
       #define BCM2835_GPPUPPDN3   0x00f0 /* Pin pull-up/down for pins 57:48 */
       #define BCM2835_GPIO_PUD_ERROR   0x08
       #define BCM2835_PADS_GPIO_0_27   0x002c
       #define BCM2835_PADS_GPIO_28_45   0x0030
       #define BCM2835_PADS_GPIO_46_53   0x0034
       #define BCM2835_PAD_PASSWRD   (0x5A << 24)
       #define BCM2835_PAD_SLEW_RATE_UNLIMITED   0x10
       #define BCM2835_PAD_HYSTERESIS_ENABLED   0x08
       #define BCM2835_PAD_DRIVE_2mA   0x00
       #define BCM2835_PAD_DRIVE_4mA   0x01
       #define BCM2835_PAD_DRIVE_6mA   0x02
       #define BCM2835_PAD_DRIVE_8mA   0x03
       #define BCM2835_PAD_DRIVE_10mA   0x04
       #define BCM2835_PAD_DRIVE_12mA   0x05
       #define BCM2835_PAD_DRIVE_14mA   0x06
       #define BCM2835_PAD_DRIVE_16mA   0x07
       #define BCM2835_AUX_IRQ   0x0000
       #define BCM2835_AUX_ENABLE   0x0004
       #define BCM2835_AUX_ENABLE_UART1   0x01
       #define BCM2835_AUX_ENABLE_SPI0   0x02
       #define BCM2835_AUX_ENABLE_SPI1   0x04
       #define BCM2835_AUX_SPI_CNTL0   0x0000
       #define BCM2835_AUX_SPI_CNTL1   0x0004
       #define BCM2835_AUX_SPI_STAT   0x0008
       #define BCM2835_AUX_SPI_PEEK   0x000C
       #define BCM2835_AUX_SPI_IO   0x0020
       #define BCM2835_AUX_SPI_TXHOLD   0x0030
       #define BCM2835_AUX_SPI_CLOCK_MIN   30500
       #define BCM2835_AUX_SPI_CLOCK_MAX   125000000
       #define BCM2835_AUX_SPI_CNTL0_SPEED   0xFFF00000
       #define BCM2835_AUX_SPI_CNTL0_SPEED_MAX   0xFFF
       #define BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT   20
       #define BCM2835_AUX_SPI_CNTL0_CS0_N   0x000C0000
       #define BCM2835_AUX_SPI_CNTL0_CS1_N   0x000A0000
       #define BCM2835_AUX_SPI_CNTL0_CS2_N   0x00060000
       #define BCM2835_AUX_SPI_CNTL0_POSTINPUT   0x00010000
       #define BCM2835_AUX_SPI_CNTL0_VAR_CS   0x00008000
       #define BCM2835_AUX_SPI_CNTL0_VAR_WIDTH   0x00004000
       #define BCM2835_AUX_SPI_CNTL0_DOUTHOLD   0x00003000
       #define BCM2835_AUX_SPI_CNTL0_ENABLE   0x00000800
       #define BCM2835_AUX_SPI_CNTL0_CPHA_IN   0x00000400
       #define BCM2835_AUX_SPI_CNTL0_CLEARFIFO   0x00000200
       #define BCM2835_AUX_SPI_CNTL0_CPHA_OUT   0x00000100
       #define BCM2835_AUX_SPI_CNTL0_CPOL   0x00000080
       #define BCM2835_AUX_SPI_CNTL0_MSBF_OUT   0x00000040
       #define BCM2835_AUX_SPI_CNTL0_SHIFTLEN   0x0000003F
       #define BCM2835_AUX_SPI_CNTL1_CSHIGH   0x00000700
       #define BCM2835_AUX_SPI_CNTL1_IDLE   0x00000080
       #define BCM2835_AUX_SPI_CNTL1_TXEMPTY   0x00000040
       #define BCM2835_AUX_SPI_CNTL1_MSBF_IN   0x00000002
       #define BCM2835_AUX_SPI_CNTL1_KEEP_IN   0x00000001
       #define BCM2835_AUX_SPI_STAT_TX_LVL   0xF0000000
       #define BCM2835_AUX_SPI_STAT_RX_LVL   0x00F00000
       #define BCM2835_AUX_SPI_STAT_TX_FULL   0x00000400
       #define BCM2835_AUX_SPI_STAT_TX_EMPTY   0x00000200
       #define BCM2835_AUX_SPI_STAT_RX_FULL   0x00000100
       #define BCM2835_AUX_SPI_STAT_RX_EMPTY   0x00000080
       #define BCM2835_AUX_SPI_STAT_BUSY   0x00000040
       #define BCM2835_AUX_SPI_STAT_BITCOUNT   0x0000003F
       #define BCM2835_SPI0_CS   0x0000
       #define BCM2835_SPI0_FIFO   0x0004
       #define BCM2835_SPI0_CLK   0x0008
       #define BCM2835_SPI0_DLEN   0x000c
       #define BCM2835_SPI0_LTOH   0x0010
       #define BCM2835_SPI0_DC   0x0014
       #define BCM2835_SPI0_CS_LEN_LONG   0x02000000
       #define BCM2835_SPI0_CS_DMA_LEN   0x01000000
       #define BCM2835_SPI0_CS_CSPOL2   0x00800000
       #define BCM2835_SPI0_CS_CSPOL1   0x00400000
       #define BCM2835_SPI0_CS_CSPOL0   0x00200000
       #define BCM2835_SPI0_CS_RXF   0x00100000
       #define BCM2835_SPI0_CS_RXR   0x00080000
       #define BCM2835_SPI0_CS_TXD   0x00040000
       #define BCM2835_SPI0_CS_RXD   0x00020000
       #define BCM2835_SPI0_CS_DONE   0x00010000
       #define BCM2835_SPI0_CS_TE_EN   0x00008000
       #define BCM2835_SPI0_CS_LMONO   0x00004000
       #define BCM2835_SPI0_CS_LEN   0x00002000
       #define BCM2835_SPI0_CS_REN   0x00001000
       #define BCM2835_SPI0_CS_ADCS   0x00000800
       #define BCM2835_SPI0_CS_INTR   0x00000400
       #define BCM2835_SPI0_CS_INTD   0x00000200
       #define BCM2835_SPI0_CS_DMAEN   0x00000100
       #define BCM2835_SPI0_CS_TA   0x00000080
       #define BCM2835_SPI0_CS_CSPOL   0x00000040
       #define BCM2835_SPI0_CS_CLEAR   0x00000030
       #define BCM2835_SPI0_CS_CLEAR_RX   0x00000020
       #define BCM2835_SPI0_CS_CLEAR_TX   0x00000010
       #define BCM2835_SPI0_CS_CPOL   0x00000008
       #define BCM2835_SPI0_CS_CPHA   0x00000004
       #define BCM2835_SPI0_CS_CS   0x00000003
       #define BCM2835_BSC_C   0x0000
       #define BCM2835_BSC_S   0x0004
       #define BCM2835_BSC_DLEN   0x0008
       #define BCM2835_BSC_A   0x000c
       #define BCM2835_BSC_FIFO   0x0010
       #define BCM2835_BSC_DIV   0x0014
       #define BCM2835_BSC_DEL   0x0018
       #define BCM2835_BSC_CLKT   0x001c
       #define BCM2835_BSC_C_I2CEN   0x00008000
       #define BCM2835_BSC_C_INTR   0x00000400
       #define BCM2835_BSC_C_INTT   0x00000200
       #define BCM2835_BSC_C_INTD   0x00000100
       #define BCM2835_BSC_C_ST   0x00000080
       #define BCM2835_BSC_C_CLEAR_1   0x00000020
       #define BCM2835_BSC_C_CLEAR_2   0x00000010
       #define BCM2835_BSC_C_READ   0x00000001
       #define BCM2835_BSC_S_CLKT   0x00000200
       #define BCM2835_BSC_S_ERR   0x00000100
       #define BCM2835_BSC_S_RXF   0x00000080
       #define BCM2835_BSC_S_TXE   0x00000040
       #define BCM2835_BSC_S_RXD   0x00000020
       #define BCM2835_BSC_S_TXD   0x00000010
       #define BCM2835_BSC_S_RXR   0x00000008
       #define BCM2835_BSC_S_TXW   0x00000004
       #define BCM2835_BSC_S_DONE   0x00000002
       #define BCM2835_BSC_S_TA   0x00000001
       #define BCM2835_BSC_FIFO_SIZE   16
       #define BCM2835_SMI_CS   0          /*! < Control and status register > */
       #define BCM2835_SMI_LENGTH   1          /*! < Transfer length register > */
       #define BCM2835_SMI_ADRS   2          /*! < Transfer address register > */
       #define BCM2835_SMI_DATA   3          /*! < Transfer data register > */
       #define BCM2835_SMI_READ0   4          /*! < Read  settings 0 register > */
       #define BCM2835_SMI_WRITE0   5          /*! < Write settings 0 register > */
       #define BCM2835_SMI_READ1   6          /*! < Read  settings 1 register > */
       #define BCM2835_SMI_WRITE1   7          /*! < Write settings 1 register > */
       #define BCM2835_SMI_READ2   8          /*! < Read  settings 2 register > */
       #define BCM2835_SMI_WRITE2   9          /*! < Write settings 2 register > */
       #define BCM2835_SMI_READ3   10          /*! < Read  settings 3 register > */
       #define BCM2835_SMI_WRITE3   11          /*! < Write settings 3 register > */
       #define BCM2835_SMI_DMAC   12          /*! < DMA control register > */
       #define BCM2835_SMI_DIRCS   13          /*! < Direct control register > */
       #define BCM2835_SMI_DIRADDR   14          /*! < Direct access address register > */
       #define BCM2835_SMI_DIRDATA   15          /*! < Direct access data register > */
       #define BCM2835_SMI_RW_WIDTH_MSK   0xC0000000 /*! < Data width mask > */
       #define BCM2835_SMI_RW_WID8   0x00000000 /*! < Data width 8 bits > */
       #define BCM2835_SMI_RW_WID16   0x40000000 /*! < Data width 16 bits > */
       #define BCM2835_SMI_RW_WID18   0x80000000 /*! < Data width 18 bits > */
       #define BCM2835_SMI_RW_WID9   0xC0000000 /*! < Data width 9 bits > */
       #define BCM2835_SMI_RW_SETUP_MSK   0x3F000000 /*! < Setup cycles (6 bits) > */
       #define BCM2835_SMI_RW_SETUP_LS   24         /*! < Shift for setup cycles > */
       #define BCM2835_SMI_RW_MODE68   0x00800000 /*! < Run cycle motorola mode > */
       #define BCM2835_SMI_RW_MODE80   0x00000000 /*! < Run cycle intel mode > */
       #define BCM2835_SMI_READ_FSETUP   0x00400000 /*! < Read : Setup only for first cycle > */
       #define BCM2835_SMI_WRITE_SWAP   0x00400000 /*! < Write : swap pixel data > */
       #define BCM2835_SMI_RW_HOLD_MSK   0x003F0000 /*! < Hold cycles (6 bits) > */
       #define BCM2835_SMI_RW_HOLD_LS   16         /*! < Shift for hold cycles > */
       #define BCM2835_SMI_RW_PACEALL   0x00008000 /*! < Apply pacing always > */
       #define BCM2835_SMI_RW_PACE_MSK   0x00007F00 /*! < Pace cycles (7 bits) > */
       #define BCM2835_SMI_RW_PACE_LS   8          /*! < Shift for pace cycles > */
       #define BCM2835_SMI_RW_DREQ   0x00000080 /*! < Use DMA req on read/write > */
       #define BCM2835_SMI_RW_STROBE_MSK   0x0000007F /*! < Strobe cycles (7 bits) > */
       #define BCM2835_SMI_RW_STROBE_LS   0          /*! < Shift for strobe cycles > */
       #define BCM2835_SMI_DIRCS_ENABLE   0x00000001  /*! < Set to enable SMI. 0 = Read from ext.
           devices > */
       #define BCM2835_SMI_DIRCS_START   0x00000002  /*! < Initiate SMI transfer > */
       #define BCM2835_SMI_DIRCS_DONE   0x00000004  /*! < Set if transfer has finished / Write to
           clear flag > */
       #define BCM2835_SMI_DIRCS_WRITE   0x00000008  /*! < 1 = Write to ext. devices > */
       #define BCM2835_SMI_DIRADRS_DEV_MSK   0x00000300  /*! < Timing configuration slot >  */
       #define BCM2835_SMI_DIRADRS_DEV_LS   8           /*! < Shift for configuration slot > */
       #define BCM2835_SMI_DIRADRS_DEV0   0x00000000  /*! < Use timing config slot 0 > */
       #define BCM2835_SMI_DIRADRS_DEV1   0x00000100  /*! < Use timing config slot 1 > */
       #define BCM2835_SMI_DIRADRS_DEV2   0x00000200  /*! < Use timing config slot 2 > */
       #define BCM2835_SMI_DIRADRS_DEV3   0x00000300  /*! < Use timing config slot 3 > */
       #define BCM2835_SMI_DIRADRS_MSK   0x0000003F  /*! < Adress bits SA5..SA0 > */
       #define BCM2835_SMI_DIRADRS_LS   0           /*! < Shift for address bits > */
       #define SMICLK_CNTL   (44)  /* = 0xB0 */
       #define SMICLK_DIV   (45)  /* = 0xB4 */
       #define BCM2835_ST_CS   0x0000
       #define BCM2835_ST_CLO   0x0004
       #define BCM2835_ST_CHI   0x0008

   Enumerations
       enum bcm2835RegisterBase { BCM2835_REGBASE_ST = 1, BCM2835_REGBASE_GPIO = 2,
           BCM2835_REGBASE_PWM = 3, BCM2835_REGBASE_CLK = 4, BCM2835_REGBASE_PADS = 5,
           BCM2835_REGBASE_SPI0 = 6, BCM2835_REGBASE_BSC0 = 7, BCM2835_REGBASE_BSC1 = 8,
           BCM2835_REGBASE_AUX = 9, BCM2835_REGBASE_SPI1 = 10, BCM2835_REGBASE_SMI = 11 }
           bcm2835RegisterBase Register bases for bcm2835_regbase()
       enum bcm2835FunctionSelect { BCM2835_GPIO_FSEL_INPT = 0x00, BCM2835_GPIO_FSEL_OUTP = 0x01,
           BCM2835_GPIO_FSEL_ALT0 = 0x04, BCM2835_GPIO_FSEL_ALT1 = 0x05, BCM2835_GPIO_FSEL_ALT2 =
           0x06, BCM2835_GPIO_FSEL_ALT3 = 0x07, BCM2835_GPIO_FSEL_ALT4 = 0x03,
           BCM2835_GPIO_FSEL_ALT5 = 0x02, BCM2835_GPIO_FSEL_MASK = 0x07 }
           bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel()
       enum bcm2835PUDControl { BCM2835_GPIO_PUD_OFF = 0x00, BCM2835_GPIO_PUD_DOWN = 0x01,
           BCM2835_GPIO_PUD_UP = 0x02 }
           bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud()
       enum bcm2835PadGroup { BCM2835_PAD_GROUP_GPIO_0_27 = 0, BCM2835_PAD_GROUP_GPIO_28_45 = 1,
           BCM2835_PAD_GROUP_GPIO_46_53 = 2 }
           bcm2835PadGroup Pad group specification for bcm2835_gpio_pad()
       enum RPiGPIOPin { RPI_GPIO_P1_03 = 0, RPI_GPIO_P1_05 = 1, RPI_GPIO_P1_07 = 4,
           RPI_GPIO_P1_08 = 14, RPI_GPIO_P1_10 = 15, RPI_GPIO_P1_11 = 17, RPI_GPIO_P1_12 = 18,
           RPI_GPIO_P1_13 = 21, RPI_GPIO_P1_15 = 22, RPI_GPIO_P1_16 = 23, RPI_GPIO_P1_18 = 24,
           RPI_GPIO_P1_19 = 10, RPI_GPIO_P1_21 = 9, RPI_GPIO_P1_22 = 25, RPI_GPIO_P1_23 = 11,
           RPI_GPIO_P1_24 = 8, RPI_GPIO_P1_26 = 7, RPI_V2_GPIO_P1_03 = 2, RPI_V2_GPIO_P1_05 = 3,
           RPI_V2_GPIO_P1_07 = 4, RPI_V2_GPIO_P1_08 = 14, RPI_V2_GPIO_P1_10 = 15,
           RPI_V2_GPIO_P1_11 = 17, RPI_V2_GPIO_P1_12 = 18, RPI_V2_GPIO_P1_13 = 27,
           RPI_V2_GPIO_P1_15 = 22, RPI_V2_GPIO_P1_16 = 23, RPI_V2_GPIO_P1_18 = 24,
           RPI_V2_GPIO_P1_19 = 10, RPI_V2_GPIO_P1_21 = 9, RPI_V2_GPIO_P1_22 = 25,
           RPI_V2_GPIO_P1_23 = 11, RPI_V2_GPIO_P1_24 = 8, RPI_V2_GPIO_P1_26 = 7,
           RPI_V2_GPIO_P1_29 = 5, RPI_V2_GPIO_P1_31 = 6, RPI_V2_GPIO_P1_32 = 12,
           RPI_V2_GPIO_P1_33 = 13, RPI_V2_GPIO_P1_35 = 19, RPI_V2_GPIO_P1_36 = 16,
           RPI_V2_GPIO_P1_37 = 26, RPI_V2_GPIO_P1_38 = 20, RPI_V2_GPIO_P1_40 = 21,
           RPI_V2_GPIO_P5_03 = 28, RPI_V2_GPIO_P5_04 = 29, RPI_V2_GPIO_P5_05 = 30,
           RPI_V2_GPIO_P5_06 = 31, RPI_BPLUS_GPIO_J8_03 = 2, RPI_BPLUS_GPIO_J8_05 = 3,
           RPI_BPLUS_GPIO_J8_07 = 4, RPI_BPLUS_GPIO_J8_08 = 14, RPI_BPLUS_GPIO_J8_10 = 15,
           RPI_BPLUS_GPIO_J8_11 = 17, RPI_BPLUS_GPIO_J8_12 = 18, RPI_BPLUS_GPIO_J8_13 = 27,
           RPI_BPLUS_GPIO_J8_15 = 22, RPI_BPLUS_GPIO_J8_16 = 23, RPI_BPLUS_GPIO_J8_18 = 24,
           RPI_BPLUS_GPIO_J8_19 = 10, RPI_BPLUS_GPIO_J8_21 = 9, RPI_BPLUS_GPIO_J8_22 = 25,
           RPI_BPLUS_GPIO_J8_23 = 11, RPI_BPLUS_GPIO_J8_24 = 8, RPI_BPLUS_GPIO_J8_26 = 7,
           RPI_BPLUS_GPIO_J8_29 = 5, RPI_BPLUS_GPIO_J8_31 = 6, RPI_BPLUS_GPIO_J8_32 = 12,
           RPI_BPLUS_GPIO_J8_33 = 13, RPI_BPLUS_GPIO_J8_35 = 19, RPI_BPLUS_GPIO_J8_36 = 16,
           RPI_BPLUS_GPIO_J8_37 = 26, RPI_BPLUS_GPIO_J8_38 = 20, RPI_BPLUS_GPIO_J8_40 = 21 }
           GPIO Pin Numbers.
       enum bcm2835SPIBitOrder { BCM2835_SPI_BIT_ORDER_LSBFIRST = 0,
           BCM2835_SPI_BIT_ORDER_MSBFIRST = 1 }
           bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for
           bcm2835_spi_setBitOrder()
       enum bcm2835SPIMode { BCM2835_SPI_MODE0 = 0, BCM2835_SPI_MODE1 = 1, BCM2835_SPI_MODE2 = 2,
           BCM2835_SPI_MODE3 = 3 }
           SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()
       enum bcm2835SPIChipSelect { BCM2835_SPI_CS0 = 0, BCM2835_SPI_CS1 = 1, BCM2835_SPI_CS2 = 2,
           BCM2835_SPI_CS_NONE = 3 }
           bcm2835SPIChipSelect Specify the SPI chip select pin(s)
       enum bcm2835SPIClockDivider { BCM2835_SPI_CLOCK_DIVIDER_65536 = 0,
           BCM2835_SPI_CLOCK_DIVIDER_32768 = 32768, BCM2835_SPI_CLOCK_DIVIDER_16384 = 16384,
           BCM2835_SPI_CLOCK_DIVIDER_8192 = 8192, BCM2835_SPI_CLOCK_DIVIDER_4096 = 4096,
           BCM2835_SPI_CLOCK_DIVIDER_2048 = 2048, BCM2835_SPI_CLOCK_DIVIDER_1024 = 1024,
           BCM2835_SPI_CLOCK_DIVIDER_512 = 512, BCM2835_SPI_CLOCK_DIVIDER_256 = 256,
           BCM2835_SPI_CLOCK_DIVIDER_128 = 128, BCM2835_SPI_CLOCK_DIVIDER_64 = 64,
           BCM2835_SPI_CLOCK_DIVIDER_32 = 32, BCM2835_SPI_CLOCK_DIVIDER_16 = 16,
           BCM2835_SPI_CLOCK_DIVIDER_8 = 8, BCM2835_SPI_CLOCK_DIVIDER_4 = 4,
           BCM2835_SPI_CLOCK_DIVIDER_2 = 2, BCM2835_SPI_CLOCK_DIVIDER_1 = 1 }
           bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the
           system clock. Figures below give the divider, clock period and clock frequency. Clock
           divided is based on nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on
           RPi3. It is reported that (contrary to the documentation) any even divider may used.
           The frequencies shown for each divider have been confirmed by measurement on RPi1 and
           RPi2. The system clock frequency on RPi3 is different, so the frequency you get from a
           given divider will be different. See comments in 'SPI Pins' for information about
           reliable SPI speeds. Note: it is possible to change the core clock rate of the RPi 3
           back to 250MHz, by putting
       enum bcm2835I2CClockDivider { BCM2835_I2C_CLOCK_DIVIDER_2500 = 2500,
           BCM2835_I2C_CLOCK_DIVIDER_626 = 626, BCM2835_I2C_CLOCK_DIVIDER_150 = 150,
           BCM2835_I2C_CLOCK_DIVIDER_148 = 148 }
           bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the
           system clock. Clock divided is based on nominal base clock rate of 250MHz
       enum bcm2835I2CReasonCodes { BCM2835_I2C_REASON_OK = 0x00, BCM2835_I2C_REASON_ERROR_NACK =
           0x01, BCM2835_I2C_REASON_ERROR_CLKT = 0x02, BCM2835_I2C_REASON_ERROR_DATA = 0x04,
           BCM2835_I2C_REASON_ERROR_TIMEOUT = 0x08 }
           bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and
           bcm2835_i2c_read functions.

   Variables
       off_t bcm2835_peripherals_base
       size_t bcm2835_peripherals_size
       uint32_t * bcm2835_peripherals
       volatile uint32_t * bcm2835_st
       volatile uint32_t * bcm2835_gpio
       volatile uint32_t * bcm2835_pwm
       volatile uint32_t * bcm2835_clk
       volatile uint32_t * bcm2835_pads
       volatile uint32_t * bcm2835_spi0
       volatile uint32_t * bcm2835_bsc0
       volatile uint32_t * bcm2835_bsc1
       volatile uint32_t * bcm2835_aux
       volatile uint32_t * bcm2835_spi1
       volatile uint32_t * bcm2835_smi

Detailed Description

       The values here are designed to be passed to various functions in the bcm2835 library.

Macro Definition Documentation

   #define BCM2835_AUX_BASE   0x215000
       Base Address of the AUX registers

   #define BCM2835_AUX_ENABLE_SPI0   0x02
       SPI0 (SPI1 in the device)

   #define BCM2835_AUX_ENABLE_SPI1   0x04
       SPI1 (SPI2 in the device)

   #define BCM2835_AUX_IRQ   0x0000
       xxx

   #define BCM2835_AUX_SPI_CLOCK_MAX   125000000
       125Mhz

   #define BCM2835_AUX_SPI_CLOCK_MIN   30500
       30,5kHz

   #define BCM2835_AUX_SPI_CNTL0_CS0_N   0x000C0000
       CS 0 low

   #define BCM2835_AUX_SPI_CNTL0_CS1_N   0x000A0000
       CS 1 low

   #define BCM2835_AUX_SPI_CNTL0_CS2_N   0x00060000
       CS 2 low

   #define BCM2835_AUX_SPI_IO   0x0020
       Write = TX, read=RX

   #define BCM2835_AUX_SPI_PEEK   0x000C
       Read but do not take from FF

   #define BCM2835_AUX_SPI_TXHOLD   0x0030
       Write = TX keep CS, read=RX

   #define BCM2835_BLOCK_SIZE   (4*1024)
       Size of memory block on RPi

   #define BCM2835_BSC0_BASE   0x205000
       Base Address of the BSC0 registers

   #define BCM2835_BSC1_BASE   0x804000
       Base Address of the BSC1 registers

   #define BCM2835_BSC_A   0x000c
       BSC Master Slave Address

   #define BCM2835_BSC_C   0x0000
       BSC Master Control

   #define BCM2835_BSC_C_CLEAR_1   0x00000020
       Clear FIFO Clear

   #define BCM2835_BSC_C_CLEAR_2   0x00000010
       Clear FIFO Clear

   #define BCM2835_BSC_C_I2CEN   0x00008000
       I2C Enable, 0 = disabled, 1 = enabled

   #define BCM2835_BSC_C_INTD   0x00000100
       Interrupt on DONE

   #define BCM2835_BSC_C_INTR   0x00000400
       Interrupt on RX

   #define BCM2835_BSC_C_INTT   0x00000200
       Interrupt on TX

   #define BCM2835_BSC_C_READ   0x00000001
       Read transfer

   #define BCM2835_BSC_C_ST   0x00000080
       Start transfer, 1 = Start a new transfer

   #define BCM2835_BSC_CLKT   0x001c
       BSC Master Clock Stretch Timeout

   #define BCM2835_BSC_DEL   0x0018
       BSC Master Data Delay

   #define BCM2835_BSC_DIV   0x0014
       BSC Master Clock Divider

   #define BCM2835_BSC_DLEN   0x0008
       BSC Master Data Length

   #define BCM2835_BSC_FIFO   0x0010
       BSC Master Data FIFO

   #define BCM2835_BSC_FIFO_SIZE   16
       BSC FIFO size

   #define BCM2835_BSC_S   0x0004
       BSC Master Status

   #define BCM2835_BSC_S_CLKT   0x00000200
       Clock stretch timeout

   #define BCM2835_BSC_S_DONE   0x00000002
       Transfer DONE

   #define BCM2835_BSC_S_ERR   0x00000100
       ACK error

   #define BCM2835_BSC_S_RXD   0x00000020
       RXD FIFO contains data

   #define BCM2835_BSC_S_RXF   0x00000080
       RXF FIFO full, 0 = FIFO is not full, 1 = FIFO is full

   #define BCM2835_BSC_S_RXR   0x00000008
       RXR FIFO needs reading (full)

   #define BCM2835_BSC_S_TA   0x00000001
       Transfer Active

   #define BCM2835_BSC_S_TXD   0x00000010
       TXD FIFO can accept data

   #define BCM2835_BSC_S_TXE   0x00000040
       TXE FIFO full, 0 = FIFO is not full, 1 = FIFO is full

   #define BCM2835_BSC_S_TXW   0x00000004
       TXW FIFO needs writing (full)

   #define BCM2835_CLOCK_BASE   0x101000
       Base Address of the Clock/timer registers

   #define BCM2835_CORE_CLK_HZ   250000000
       Speed of the core clock core_clk 250 MHz

   #define BCM2835_GPAFEN0   0x0088
       GPIO Pin Async. Falling Edge Detect 0

   #define BCM2835_GPAFEN1   0x008c
       GPIO Pin Async. Falling Edge Detect 1

   #define BCM2835_GPAREN0   0x007c
       GPIO Pin Async. Rising Edge Detect 0

   #define BCM2835_GPAREN1   0x0080
       GPIO Pin Async. Rising Edge Detect 1

   #define BCM2835_GPCLR0   0x0028
       GPIO Pin Output Clear 0

   #define BCM2835_GPCLR1   0x002c
       GPIO Pin Output Clear 1

   #define BCM2835_GPEDS0   0x0040
       GPIO Pin Event Detect Status 0

   #define BCM2835_GPEDS1   0x0044
       GPIO Pin Event Detect Status 1

   #define BCM2835_GPFEN0   0x0058
       GPIO Pin Falling Edge Detect Enable 0

   #define BCM2835_GPFEN1   0x005c
       GPIO Pin Falling Edge Detect Enable 1

   #define BCM2835_GPFSEL0   0x0000
       GPIO register offsets from BCM2835_GPIO_BASE. Offsets into the GPIO Peripheral block in
       bytes per 6.1 Register View GPIO Function Select 0

   #define BCM2835_GPFSEL1   0x0004
       GPIO Function Select 1

   #define BCM2835_GPFSEL2   0x0008
       GPIO Function Select 2

   #define BCM2835_GPFSEL3   0x000c
       GPIO Function Select 3

   #define BCM2835_GPFSEL4   0x0010
       GPIO Function Select 4

   #define BCM2835_GPFSEL5   0x0014
       GPIO Function Select 5

   #define BCM2835_GPHEN0   0x0064
       GPIO Pin High Detect Enable 0

   #define BCM2835_GPHEN1   0x0068
       GPIO Pin High Detect Enable 1

   #define BCM2835_GPIO_BASE   0x200000
       Base Address of the GPIO registers

   #define BCM2835_GPIO_PADS   0x100000
       Base Address of the Pads registers

   #define BCM2835_GPIO_PWM   0x20C000
       Base Address of the PWM registers

   #define BCM2835_GPLEN0   0x0070
       GPIO Pin Low Detect Enable 0

   #define BCM2835_GPLEN1   0x0074
       GPIO Pin Low Detect Enable 1

   #define BCM2835_GPLEV0   0x0034
       GPIO Pin Level 0

   #define BCM2835_GPLEV1   0x0038
       GPIO Pin Level 1

   #define BCM2835_GPPUD   0x0094
       GPIO Pin Pull-up/down Enable

   #define BCM2835_GPPUDCLK0   0x0098
       GPIO Pin Pull-up/down Enable Clock 0

   #define BCM2835_GPPUDCLK1   0x009c
       GPIO Pin Pull-up/down Enable Clock 1

   #define BCM2835_GPREN0   0x004c
       GPIO Pin Rising Edge Detect Enable 0

   #define BCM2835_GPREN1   0x0050
       GPIO Pin Rising Edge Detect Enable 1

   #define BCM2835_GPSET0   0x001c
       GPIO Pin Output Set 0

   #define BCM2835_GPSET1   0x0020
       GPIO Pin Output Set 1

   #define BCM2835_PAD_DRIVE_10mA   0x04
       10mA drive current

   #define BCM2835_PAD_DRIVE_12mA   0x05
       12mA drive current

   #define BCM2835_PAD_DRIVE_14mA   0x06
       14mA drive current

   #define BCM2835_PAD_DRIVE_16mA   0x07
       16mA drive current

   #define BCM2835_PAD_DRIVE_2mA   0x00
       2mA drive current

   #define BCM2835_PAD_DRIVE_4mA   0x01
       4mA drive current

   #define BCM2835_PAD_DRIVE_6mA   0x02
       6mA drive current

   #define BCM2835_PAD_DRIVE_8mA   0x03
       8mA drive current

   #define BCM2835_PAD_HYSTERESIS_ENABLED   0x08
       Hysteresis enabled

   #define BCM2835_PAD_PASSWRD   (0x5A << 24)
       Pad Control masks Password to enable setting pad mask

   #define BCM2835_PAD_SLEW_RATE_UNLIMITED   0x10
       Slew rate unlimited

   #define BCM2835_PADS_GPIO_0_27   0x002c
       Pad control register offsets from BCM2835_GPIO_PADS Pad control register for pads 0 to 27

   #define BCM2835_PADS_GPIO_28_45   0x0030
       Pad control register for pads 28 to 45

   #define BCM2835_PADS_GPIO_46_53   0x0034
       Pad control register for pads 46 to 53

   #define BCM2835_PAGE_SIZE   (4*1024)
       Size of memory page on RPi

   #define BCM2835_PERI_BASE   0x20000000
       Physical addresses for various peripheral register sets Base Physical Address of the BCM
       2835 peripheral registers Note this is different for the RPi2 BCM2836, where this is
       derived from /proc/device-tree/soc/ranges If /proc/device-tree/soc/ranges exists on a RPi
       1 OS, it would be expected to contain the following numbers:

       Peripherals block base address on RPi 1

   #define BCM2835_PERI_SIZE   0x01000000
       Size of the peripherals block on RPi 1

   #define BCM2835_RPI2_PERI_BASE   0x3F000000
       Alternate base address for RPI 2 / 3

   #define BCM2835_RPI4_PERI_BASE   0xFE000000
       Alternate base address for RPI 4

   #define BCM2835_RPI4_PERI_SIZE   0x01800000
       Alternate size for RPI 4

   #define BCM2835_SMI_BASE   0x600000
       Base address of the SMI registers

   #define BCM2835_SPI0_BASE   0x204000
       Base Address of the SPI0 registers

   #define BCM2835_SPI0_CLK   0x0008
       SPI Master Clock Divider

   #define BCM2835_SPI0_CS   0x0000
       SPI Master Control and Status

   #define BCM2835_SPI0_CS_ADCS   0x00000800
       ADCS Automatically Deassert Chip Select

   #define BCM2835_SPI0_CS_CLEAR   0x00000030
       Clear FIFO Clear RX and TX

   #define BCM2835_SPI0_CS_CLEAR_RX   0x00000020
       Clear FIFO Clear RX

   #define BCM2835_SPI0_CS_CLEAR_TX   0x00000010
       Clear FIFO Clear TX

   #define BCM2835_SPI0_CS_CPHA   0x00000004
       Clock Phase

   #define BCM2835_SPI0_CS_CPOL   0x00000008
       Clock Polarity

   #define BCM2835_SPI0_CS_CS   0x00000003
       Chip Select

   #define BCM2835_SPI0_CS_CSPOL   0x00000040
       Chip Select Polarity

   #define BCM2835_SPI0_CS_CSPOL0   0x00200000
       Chip Select 0 Polarity

   #define BCM2835_SPI0_CS_CSPOL1   0x00400000
       Chip Select 1 Polarity

   #define BCM2835_SPI0_CS_CSPOL2   0x00800000
       Chip Select 2 Polarity

   #define BCM2835_SPI0_CS_DMA_LEN   0x01000000
       Enable DMA mode in Lossi mode

   #define BCM2835_SPI0_CS_DMAEN   0x00000100
       DMAEN DMA Enable

   #define BCM2835_SPI0_CS_DONE   0x00010000
       Done transfer Done

   #define BCM2835_SPI0_CS_INTD   0x00000200
       INTD Interrupt on Done

   #define BCM2835_SPI0_CS_INTR   0x00000400
       INTR Interrupt on RXR

   #define BCM2835_SPI0_CS_LEN   0x00002000
       LEN LoSSI enable

   #define BCM2835_SPI0_CS_LEN_LONG   0x02000000
       Enable Long data word in Lossi mode if DMA_LEN is set

   #define BCM2835_SPI0_CS_LMONO   0x00004000
       Unused

   #define BCM2835_SPI0_CS_REN   0x00001000
       REN Read Enable

   #define BCM2835_SPI0_CS_RXD   0x00020000
       RXD RX FIFO contains Data

   #define BCM2835_SPI0_CS_RXF   0x00100000
       RXF - RX FIFO Full

   #define BCM2835_SPI0_CS_RXR   0x00080000
       RXR RX FIFO needs Reading (full)

   #define BCM2835_SPI0_CS_TA   0x00000080
       Transfer Active

   #define BCM2835_SPI0_CS_TE_EN   0x00008000
       Unused

   #define BCM2835_SPI0_CS_TXD   0x00040000
       TXD TX FIFO can accept Data

   #define BCM2835_SPI0_DC   0x0014
       SPI DMA DREQ Controls

   #define BCM2835_SPI0_DLEN   0x000c
       SPI Master Data Length

   #define BCM2835_SPI0_FIFO   0x0004
       SPI Master TX and RX FIFOs

   #define BCM2835_SPI0_LTOH   0x0010
       SPI LOSSI mode TOH

   #define BCM2835_SPI1_BASE   0x215080
       Base Address of the AUX_SPI1 registers

   #define BCM2835_SPI2_BASE   0x2150C0
       Base Address of the AUX_SPI2 registers

   #define BCM2835_ST_BASE   0x3000
       Offsets for the bases of various peripherals within the peripherals block / Base Address
       of the System Timer registers

   #define BCM2835_ST_CHI   0x0008
       System Timer Counter Upper 32 bits

   #define BCM2835_ST_CLO   0x0004
       System Timer Counter Lower 32 bits

   #define BCM2835_ST_CS   0x0000
       System Timer Control/Status

   #define BMC2835_RPI2_DT_FILENAME   '/proc/device-tree/soc/ranges'
       On all recent OSs, the base of the peripherals is read from a /proc file

   #define HIGH   0x1
       This means pin HIGH, true, 3.3volts on a pin.

   #define LOW   0x0
       This means pin LOW, false, 0volts on a pin.

   #define MIN(a, b)   (a < b ? a : b)
       Return the minimum of 2 numbers

Enumeration Type Documentation

   enum bcm2835FunctionSelect
       bcm2835PortFunction Port function select modes for bcm2835_gpio_fsel()

       Enumerator

       BCM2835_GPIO_FSEL_INPT
              Input 0b000

       BCM2835_GPIO_FSEL_OUTP
              Output 0b001

       BCM2835_GPIO_FSEL_ALT0
              Alternate function 0 0b100

       BCM2835_GPIO_FSEL_ALT1
              Alternate function 1 0b101

       BCM2835_GPIO_FSEL_ALT2
              Alternate function 2 0b110,

       BCM2835_GPIO_FSEL_ALT3
              Alternate function 3 0b111

       BCM2835_GPIO_FSEL_ALT4
              Alternate function 4 0b011

       BCM2835_GPIO_FSEL_ALT5
              Alternate function 5 0b010

       BCM2835_GPIO_FSEL_MASK
              Function select bits mask 0b111

   enum bcm2835I2CClockDivider
       bcm2835I2CClockDivider Specifies the divider used to generate the I2C clock from the
       system clock. Clock divided is based on nominal base clock rate of 250MHz

       Enumerator

       BCM2835_I2C_CLOCK_DIVIDER_2500
              2500 = 10us = 100 kHz

       BCM2835_I2C_CLOCK_DIVIDER_626
              622 = 2.504us = 399.3610 kHz

       BCM2835_I2C_CLOCK_DIVIDER_150
              150 = 60ns = 1.666 MHz (default at reset)

       BCM2835_I2C_CLOCK_DIVIDER_148
              148 = 59ns = 1.689 MHz

   enum bcm2835I2CReasonCodes
       bcm2835I2CReasonCodes Specifies the reason codes for the bcm2835_i2c_write and
       bcm2835_i2c_read functions.

       Enumerator

       BCM2835_I2C_REASON_OK
              Success

       BCM2835_I2C_REASON_ERROR_NACK
              Received a NACK

       BCM2835_I2C_REASON_ERROR_CLKT
              Received Clock Stretch Timeout

       BCM2835_I2C_REASON_ERROR_DATA
              Not all data is sent / received

       BCM2835_I2C_REASON_ERROR_TIMEOUT
              Time out occurred during sending

   enum bcm2835PadGroup
       bcm2835PadGroup Pad group specification for bcm2835_gpio_pad()

       Enumerator

       BCM2835_PAD_GROUP_GPIO_0_27
              Pad group for GPIO pads 0 to 27

       BCM2835_PAD_GROUP_GPIO_28_45
              Pad group for GPIO pads 28 to 45

       BCM2835_PAD_GROUP_GPIO_46_53
              Pad group for GPIO pads 46 to 53

   enum bcm2835PUDControl
       bcm2835PUDControl Pullup/Pulldown defines for bcm2835_gpio_pud()

       Enumerator

       BCM2835_GPIO_PUD_OFF
              Off ? disable pull-up/down 0b00

       BCM2835_GPIO_PUD_DOWN
              Enable Pull Down control 0b01

       BCM2835_GPIO_PUD_UP
              Enable Pull Up control 0b10

   enum bcm2835RegisterBase
       bcm2835RegisterBase Register bases for bcm2835_regbase()

       Enumerator

       BCM2835_REGBASE_ST
              Base of the ST (System Timer) registers.

       BCM2835_REGBASE_GPIO
              Base of the GPIO registers.

       BCM2835_REGBASE_PWM
              Base of the PWM registers.

       BCM2835_REGBASE_CLK
              Base of the CLK registers.

       BCM2835_REGBASE_PADS
              Base of the PADS registers.

       BCM2835_REGBASE_SPI0
              Base of the SPI0 registers.

       BCM2835_REGBASE_BSC0
              Base of the BSC0 registers.

       BCM2835_REGBASE_BSC1
              Base of the BSC1 registers.

       BCM2835_REGBASE_AUX
              Base of the AUX registers.

       BCM2835_REGBASE_SPI1
              Base of the SPI1 registers.

       BCM2835_REGBASE_SMI
              Base of the SMI registers.

   enum bcm2835SPIBitOrder
       bcm2835SPIBitOrder SPI Bit order Specifies the SPI data bit ordering for
       bcm2835_spi_setBitOrder()

       Enumerator

       BCM2835_SPI_BIT_ORDER_LSBFIRST
              LSB First

       BCM2835_SPI_BIT_ORDER_MSBFIRST
              MSB First

   enum bcm2835SPIChipSelect
       bcm2835SPIChipSelect Specify the SPI chip select pin(s)

       Enumerator

       BCM2835_SPI_CS0
              Chip Select 0

       BCM2835_SPI_CS1
              Chip Select 1

       BCM2835_SPI_CS2
              Chip Select 2 (ie pins CS1 and CS2 are asserted)

       BCM2835_SPI_CS_NONE
              No CS, control it yourself

   enum bcm2835SPIClockDivider
       bcm2835SPIClockDivider Specifies the divider used to generate the SPI clock from the
       system clock. Figures below give the divider, clock period and clock frequency. Clock
       divided is based on nominal core clock rate of 250MHz on RPi1 and RPi2, and 400MHz on
       RPi3. It is reported that (contrary to the documentation) any even divider may used. The
       frequencies shown for each divider have been confirmed by measurement on RPi1 and RPi2.
       The system clock frequency on RPi3 is different, so the frequency you get from a given
       divider will be different. See comments in 'SPI Pins' for information about reliable SPI
       speeds. Note: it is possible to change the core clock rate of the RPi 3 back to 250MHz, by
       putting

       core_freq=250

        in the config.txt

       Enumerator

       BCM2835_SPI_CLOCK_DIVIDER_65536
              65536 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_32768
              32768 = 7.629394531kHz on Rpi2, 12.20703125kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_16384
              16384 = 15.25878906kHz on Rpi2, 24.4140625kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_8192
              8192 = 30.51757813kHz on Rpi2, 48.828125kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_4096
              4096 = 61.03515625kHz on Rpi2, 97.65625kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_2048
              2048 = 122.0703125kHz on Rpi2, 195.3125kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_1024
              1024 = 244.140625kHz on Rpi2, 390.625kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_512
              512 = 488.28125kHz on Rpi2, 781.25kHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_256
              256 = 976.5625kHz on Rpi2, 1.5625MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_128
              128 = 1.953125MHz on Rpi2, 3.125MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_64
              64 = 3.90625MHz on Rpi2, 6.250MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_32
              32 = 7.8125MHz on Rpi2, 12.5MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_16
              16 = 15.625MHz on Rpi2, 25MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_8
              8 = 31.25MHz on Rpi2, 50MHz on RPI3

       BCM2835_SPI_CLOCK_DIVIDER_4
              4 = 62.5MHz on Rpi2, 100MHz on RPI3. Dont expect this speed to work reliably.

       BCM2835_SPI_CLOCK_DIVIDER_2
              2 = 125MHz on Rpi2, 200MHz on RPI3, fastest you can get. Dont expect this speed to
              work reliably.

       BCM2835_SPI_CLOCK_DIVIDER_1
              1 = 3.814697260kHz on Rpi2, 6.1035156kHz on RPI3, same as 0/65536

   enum bcm2835SPIMode
       SPI Data mode Specify the SPI data mode to be passed to bcm2835_spi_setDataMode()

       Enumerator

       BCM2835_SPI_MODE0
              CPOL = 0, CPHA = 0

       BCM2835_SPI_MODE1
              CPOL = 0, CPHA = 1

       BCM2835_SPI_MODE2
              CPOL = 1, CPHA = 0

       BCM2835_SPI_MODE3
              CPOL = 1, CPHA = 1

   enum RPiGPIOPin
       GPIO Pin Numbers. Here we define Raspberry Pin GPIO pins on P1 in terms of the underlying
       BCM GPIO pin numbers. These can be passed as a pin number to any function requiring a pin.
       Not all pins on the RPi 26 bin IDE plug are connected to GPIO pins and some can adopt an
       alternate function. RPi version 2 has some slightly different pinouts, and these are
       values RPI_V2_*. RPi B+ has yet differnet pinouts and these are defined in RPI_BPLUS_*. At
       bootup, pins 8 and 10 are set to UART0_TXD, UART0_RXD (ie the alt0 function) respectively
       When SPI0 is in use (ie after bcm2835_spi_begin()), SPI0 pins are dedicated to SPI and
       cant be controlled independently. If you are using the RPi Compute Module, just use the
       GPIO number: there is no need to use one of these symbolic names

       Enumerator

       RPI_GPIO_P1_03
              Version 1, Pin P1-03

       RPI_GPIO_P1_05
              Version 1, Pin P1-05

       RPI_GPIO_P1_07
              Version 1, Pin P1-07

       RPI_GPIO_P1_08
              Version 1, Pin P1-08, defaults to alt function 0 UART0_TXD

       RPI_GPIO_P1_10
              Version 1, Pin P1-10, defaults to alt function 0 UART0_RXD

       RPI_GPIO_P1_11
              Version 1, Pin P1-11

       RPI_GPIO_P1_12
              Version 1, Pin P1-12, can be PWM channel 0 in ALT FUN 5

       RPI_GPIO_P1_13
              Version 1, Pin P1-13

       RPI_GPIO_P1_15
              Version 1, Pin P1-15

       RPI_GPIO_P1_16
              Version 1, Pin P1-16

       RPI_GPIO_P1_18
              Version 1, Pin P1-18

       RPI_GPIO_P1_19
              Version 1, Pin P1-19, MOSI when SPI0 in use

       RPI_GPIO_P1_21
              Version 1, Pin P1-21, MISO when SPI0 in use

       RPI_GPIO_P1_22
              Version 1, Pin P1-22

       RPI_GPIO_P1_23
              Version 1, Pin P1-23, CLK when SPI0 in use

       RPI_GPIO_P1_24
              Version 1, Pin P1-24, CE0 when SPI0 in use

       RPI_GPIO_P1_26
              Version 1, Pin P1-26, CE1 when SPI0 in use

       RPI_V2_GPIO_P1_03
              Version 2, Pin P1-03

       RPI_V2_GPIO_P1_05
              Version 2, Pin P1-05

       RPI_V2_GPIO_P1_07
              Version 2, Pin P1-07

       RPI_V2_GPIO_P1_08
              Version 2, Pin P1-08, defaults to alt function 0 UART0_TXD

       RPI_V2_GPIO_P1_10
              Version 2, Pin P1-10, defaults to alt function 0 UART0_RXD

       RPI_V2_GPIO_P1_11
              Version 2, Pin P1-11

       RPI_V2_GPIO_P1_12
              Version 2, Pin P1-12, can be PWM channel 0 in ALT FUN 5

       RPI_V2_GPIO_P1_13
              Version 2, Pin P1-13

       RPI_V2_GPIO_P1_15
              Version 2, Pin P1-15

       RPI_V2_GPIO_P1_16
              Version 2, Pin P1-16

       RPI_V2_GPIO_P1_18
              Version 2, Pin P1-18

       RPI_V2_GPIO_P1_19
              Version 2, Pin P1-19, MOSI when SPI0 in use

       RPI_V2_GPIO_P1_21
              Version 2, Pin P1-21, MISO when SPI0 in use

       RPI_V2_GPIO_P1_22
              Version 2, Pin P1-22

       RPI_V2_GPIO_P1_23
              Version 2, Pin P1-23, CLK when SPI0 in use

       RPI_V2_GPIO_P1_24
              Version 2, Pin P1-24, CE0 when SPI0 in use

       RPI_V2_GPIO_P1_26
              Version 2, Pin P1-26, CE1 when SPI0 in use

       RPI_V2_GPIO_P1_29
              Version 2, Pin P1-29

       RPI_V2_GPIO_P1_31
              Version 2, Pin P1-31

       RPI_V2_GPIO_P1_32
              Version 2, Pin P1-32

       RPI_V2_GPIO_P1_33
              Version 2, Pin P1-33

       RPI_V2_GPIO_P1_35
              Version 2, Pin P1-35, can be PWM channel 1 in ALT FUN 5

       RPI_V2_GPIO_P1_36
              Version 2, Pin P1-36

       RPI_V2_GPIO_P1_37
              Version 2, Pin P1-37

       RPI_V2_GPIO_P1_38
              Version 2, Pin P1-38

       RPI_V2_GPIO_P1_40
              Version 2, Pin P1-40

       RPI_V2_GPIO_P5_03
              Version 2, Pin P5-03

       RPI_V2_GPIO_P5_04
              Version 2, Pin P5-04

       RPI_V2_GPIO_P5_05
              Version 2, Pin P5-05

       RPI_V2_GPIO_P5_06
              Version 2, Pin P5-06

       RPI_BPLUS_GPIO_J8_03
              B+, Pin J8-03

       RPI_BPLUS_GPIO_J8_05
              B+, Pin J8-05

       RPI_BPLUS_GPIO_J8_07
              B+, Pin J8-07

       RPI_BPLUS_GPIO_J8_08
              B+, Pin J8-08, defaults to alt function 0 UART0_TXD

       RPI_BPLUS_GPIO_J8_10
              B+, Pin J8-10, defaults to alt function 0 UART0_RXD

       RPI_BPLUS_GPIO_J8_11
              B+, Pin J8-11

       RPI_BPLUS_GPIO_J8_12
              B+, Pin J8-12, can be PWM channel 0 in ALT FUN 5

       RPI_BPLUS_GPIO_J8_13
              B+, Pin J8-13

       RPI_BPLUS_GPIO_J8_15
              B+, Pin J8-15

       RPI_BPLUS_GPIO_J8_16
              B+, Pin J8-16

       RPI_BPLUS_GPIO_J8_18
              B+, Pin J8-18

       RPI_BPLUS_GPIO_J8_19
              B+, Pin J8-19, MOSI when SPI0 in use

       RPI_BPLUS_GPIO_J8_21
              B+, Pin J8-21, MISO when SPI0 in use

       RPI_BPLUS_GPIO_J8_22
              B+, Pin J8-22

       RPI_BPLUS_GPIO_J8_23
              B+, Pin J8-23, CLK when SPI0 in use

       RPI_BPLUS_GPIO_J8_24
              B+, Pin J8-24, CE0 when SPI0 in use

       RPI_BPLUS_GPIO_J8_26
              B+, Pin J8-26, CE1 when SPI0 in use

       RPI_BPLUS_GPIO_J8_29
              B+, Pin J8-29,

       RPI_BPLUS_GPIO_J8_31
              B+, Pin J8-31,

       RPI_BPLUS_GPIO_J8_32
              B+, Pin J8-32,

       RPI_BPLUS_GPIO_J8_33
              B+, Pin J8-33,

       RPI_BPLUS_GPIO_J8_35
              B+, Pin J8-35, can be PWM channel 1 in ALT FUN 5

       RPI_BPLUS_GPIO_J8_36
              B+, Pin J8-36,

       RPI_BPLUS_GPIO_J8_37
              B+, Pin J8-37,

       RPI_BPLUS_GPIO_J8_38
              B+, Pin J8-38,

       RPI_BPLUS_GPIO_J8_40
              B+, Pin J8-40,

Variable Documentation

   volatile uint32_t* bcm2835_aux [extern]
       Base of the AUX registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_bsc0 [extern]
       Base of the BSC0 registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_bsc1 [extern]
       Base of the BSC1 registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_clk [extern]
       Base of the CLK registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_gpio [extern]
       Base of the GPIO registers. Available after bcm2835_init has been called

   volatile uint32_t* bcm2835_pads [extern]
       Base of the PADS registers. Available after bcm2835_init has been called (as root)

   uint32_t* bcm2835_peripherals [extern]
       Virtual memory address of the mapped peripherals block

   off_t bcm2835_peripherals_base [extern]
       Physical address and size of the peripherals block May be overridden on RPi2

   size_t bcm2835_peripherals_size [extern]
       Size of the peripherals block to be mapped

   volatile uint32_t* bcm2835_pwm [extern]
       Base of the PWM registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_smi [extern]
       Base of SMI registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_spi0 [extern]
       Base of the SPI0 registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_spi1 [extern]
       Base of the SPI1 registers. Available after bcm2835_init has been called (as root)

   volatile uint32_t* bcm2835_st [extern]
       Base of the ST (System Timer) registers. Available after bcm2835_init has been called (as
       root)

Author

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