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Provided by: alliance_5.0-20110203-4_i386

NAME

       BooG - Binding and Optimizing On Gates.

SYNOPSIS

       boog  [-hmxold] input_file output_file  [lax_file]

DESCRIPTION

       boog  is  a  mapper  of  a  behavioural  description  onto a predefined
       standard cell library as SXLIB.  It is the second  step  of  the  logic
       synthesis: it builds a gate network using a standard cell library.

         Input file description
       The  logic level behavioural description (.vbe file) uses the same VHDL
       subset as the logic simulator asimut,  the  FSM  synthesizer  syf,  the
       functional  abstractor  yagle  and the formal prover proof (for further
       information about the subset of VHDL, see the "vbe" manual).
       Some constraints due to hardware mapping exist.  These  attributes  are
       only  supported  by  technology mapping onto a standard cell library as
       sxlib.
       For the register signal description, only one condition statement  must
       appear. STABLE must be strictely used as a negativ motion and joined to
       clock setup value. Setup can be on high or low value, but it  would  be
       worthy to choose it accordingly with hardware register cell.
       # Example
               label: BLOCK (NOT ck 'STABLE and ck='1')
               BEGIN
                   reg <= GUARDED expr;
               END BLOCK;

       You can also put a write enable condition to your register:
               label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
               BEGIN
                   reg <= GUARDED expr;
               END BLOCK;

       A  special  feature  has been introduced in the VHDL subset in order to
       allow the don't care description  for  external  outputs  and  internal
       registers  :  A  bit  signal  can  take  the  'd' value.  This value is
       interpreted as a '0' by the logic simulator asimut.   Don't  Cares  are
       automatically generated by syf in the resulting '.vbe' file.

         Output file description
       A  pure  standard  cell  netlist  is  produced  by  boog.  This file is
       destinated for /fBloon/fP alliance utility to improve RC  delays.   Any
       equipotential  keeps  its  name from connector to connector. In trouble
       case, buffers are inserted to respect this VHDL constraint.

         lax Parameter file description
       The lax file is common with other logic synthesis tools and is used for
       driving the synthesis process.  See lax(5) manual for more detail.

       lax  uses  a  lot  of  parameters  to guide every step of the synthesis
       process.  Some parameters are globally used (for example,  optimization
       level  whereas  others  are specifically used (load capacitance for the
       netlist optimization only).  Here is the  default  lax  file  (see  the
       user's  manual  for  further information about the syntax of the '.lax'
       file):

          Optimization mode = 2 (50% area - 50% delay)
          Input impedance = 0
          Output capacitance = 0
          Delayed input = none
          Auxiliary signal saved = none

         Mapping with a standard cell library
       Every cell appearing  in  the  directory  defined  by  the  environment
       variable MBK_TARGET_LIB may be used by boog since they are described as
       a '.vbe' file. There are some restrictions about the type of  the  cell
       used.  Every  cell  has  to  have  only  one  output.  The cell must be
       characterized. The timing and area informations required  by  boog  are
       specified in the "generic" clause of the ".vbe" file.

OPTION

       -h        Help mode. Displays possible uses of boog.

       -m optim_mode
                 Optimization  mode.  Can  be defined in lax file, it's only a
                 shortcut to define it on command line. This mode  number  has
                 an  array  defined  between  0 and 4. It indicates the way of
                 optimization the user wants. If 0 is chosen, the circuit area
                 will  be  improved. On the other hand, 4 will improve circuit
                 delays. 2 is a medium value for optimization.

       -x xsch_mode
                 Generate a '.xsc' file. It is a color map  for  each  signals
                 contained  in  output_file network. This file is used by xsch
                 to view the netlist. By choosing level 0 or 1 for  xsch_mode,
                 you  can  color respectively the critical path or all signals
                 with delay graduation.

       -o output_file
                 Just another way to show  explicitely  the  VST  output  file
                 name.

       -l lax_file
                 Just  another  way to show explicitely the LAX parameter file
                 name.

       -d debug_file
                 Generates a VBEdebug file.  It  comes  from  internal  result
                 algorithm. Users aren't concerned.

ENVIRONMENT VARIABLES

       The following environment variables have to be set before using boog :

       MBK_CATA_LIB  gives  the  auxiliary  paths  of the directories of input
              files (behavioural description).

       MBK_TARGET_LIB gives the path (single) of the directory of the selected
              standard cell library.

       MBK_OUT_LO gives the output format of the structural description.

EXAMPLE

       You can call boog as follows :
            boog alu alu

SEE ALSO

       boog(1),   boom(1),   loon(1),  lax(5),  vbe(5),  proof(1),  asimut(1),
       vhdl(5), ocp(1), nero(1), sxlib(5).