Provided by: alliance_5.0-20110203-4_i386
SYF - Finite State Machine synthesizer.
syf -a|j|m|u|o|r [-CDEOPRSTV] input_name [output_name]
syf is a Finite State Machine synthesizer. syf allows a fast
generation of VHDL Data Flow description (see vbe(5)) from a VHDL
Finite State Machine description (see fsm(5)). The input FSM
specification can use an internal STACK. Both MOORE and MEALEY FSMs
can be synthesized, with output registers if desired. For a MOORE FSM,
a timing-optimized implementation that emulates a ROM with
microsequencer is possible. A scan-path for the state registers can
also be implemented.
indicates the path to the read/write directory for the
-a Uses "Asp" as encoding algorithm.
-j Uses "Jedi" as encoding algorithm.
-m Uses "Mustang" as encoding algorithm.
-u Uses an encoding given by user through <input_name>.enc file.
In this file, a line started by a # character is a comment.
A valid line contains one state name followed by its
-o Uses the one hot encoding algorithm.
-r Uses distinct random numbers for state encoding.
-C Checks the transition's consistency.
-D With this option syf doesn't optimize unused, i.e Don't Care,
-E Saves the encoding result in the <output_name>.enc. This
file has the same syntax as <input_name>.enc file which is
used by -u option.
-O With this option syf places registers on the outputs.
-P Implements a scan-path for the state registers, stack
registers and possibly output registers. Scan-path mechanism
is directely included in states decoder. Users should use
scapin(5) for a correct insertion of a scan-path in a
netlist. Please check fsm(5) for information about scan-path
-R This option is only available for MOORE FSM. With this
option, syf emulate s a ROM with micro-sequencer
implementation : there is no combinatorial logic between the
state registers and the FSM outputs. This can be mandatory
for external timing constraints. See fsm(5) and grog(1) for
more on ROM descriptions.
-S With this option syf doesn't take into account the cost of
the transitions to compute an encoding.
-V Verbose mode on. Each step of the FSM synthesis is displayed
on the standard output, along with some statistics.
setenv MBK_WORK_LIB /alliance/tutorials/dlxm
syf is called as follow (the dlx_ctrl.fsm is already created in
syf -sE dlx_ctrl
Two files will be generated, a states encoding file dlx_ctrls.enc and a
VHDL data flow file /alliance/tutorials/dlxm/dlx_ctrls.vbe
fsm(5), vbe(5), vhdl(5), boom(1), boog(1), loon(1), scapin(1),
asimut(1), proof(1), MBK_WORK_LIB(1).