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NAME

       PAT - Pattern description format

DESCRIPTION

       The  pat  is  a  specific format used in simulation pattern´s description.  pat format has
       been designed to represent undifferently patterns to be simulated or simulation's results.
       It offers the possibility of:

       specifying the input list of the circuit: signals to be controled during the simulation by
       the user. For a circuit described in VHDL, are considered as input:

              external ports of the mode in.
              guarded external ports of the mode inout (declared with the reserved word bus).

       specifying the output list of the circuit: signals to be observed during  the  simulation.
       For a circuit described in VHDL, are considered as output:

              external  ports  of the mode out (declared either with or without the reserved word
              bus).
              external ports of the mode inout (declared either with or without the reserved word
              bus).
              internal signals of a hierarchical description.
              internal  signals of a behavioural description (declared as bus, register or simple
              signal)

       specifying a read-write format for inputs and outputs.

       forcing the value of each input.

       checking the resulted value on each output.

       changing the value of an internal register (a guarded internal signal of kind register  in
       a behavioural description).

       saving the state of the circuit.

THE FORMAT

       A  pattern file written in pat format can be divided into two parts: the declaration block
       and the description block. The instruction begin marks the end of the declaration and  the
       beginning of the description block. The instruction end; marks the end of the file.

       The declaration block is a set of input-output declaration statements.  The order of these
       declarations is important. In the description block, values will  be  associated  with  an
       input-output  in  the  order  of  their  declaration.   That  is,  the first value will be
       associated with the first declared input-output and, the last value with the last one.

       A declaration statement has of one of the two following forms :
              mode input_output_name [format] [spy_option];
              mode group_name (input_output_name, ...) [format] [spy_option];

       The second form allows the user to give a name to  a  group  of  signals.  This  group  of
       signals  will be called virtual array. Using this grouping possibility, great care must be
       taken. Two guarded outputs (of kind bus) can be grouped only if their guard expression are
       exactly the same.

       inputs    An  external  port  of  the mode in must be declared with the mode in. A guarded
                 external port of the mode inout must be declared with the mode inout.

       outputs   An external port (guarded or not) of the mode out must be declared with the mode
                 out. An unguarded external port of the mode inout must be declared with the mode
                 out. A guarded external port of the mode inout must be declared  with  the  mode
                 inout.  An  internal  signal (simple or guarded of kind bus) of a behavioural or
                 structural description must be  declared  with  the  mode  signal.  An  internal
                 register (guarded signal of kind register) is to be declared with mode register.

       The format specifies the format under which values associated with an input-output must be
       read or written. Legal formats are X for hexadecimal, O for octal and, B for  binary.  The
       binary format is the default format.

       The  input_output_name is used to identify the input-output signal.  For an external port,
       the signal´s identifier added, if the signal is an array, to its constraint (the range  of
       the   array)   constitutes   the   input-output   name.    For   an  internal  signal  the
       input_output_name is made from the concatenation of the access_path and the signal´s  name
       (identifier  and  if  needed  constraint).  The  access_path  is a string representing the
       instance where the signal is declared. It is a list of instance  names  separated  by  ´.´
       (dot).

       The  spy  option  (keyword  spy)  may  be used for outputs (out port, inout port, internal
       signal). This option makes one additional pattern be printed in the result file each  time
       an  event  occurs on this signal during the simulation and the corresponding pattern (with
       this event date) has been omitted in the input pattern file.

       Putting one  or  several  additional  ´;´  (semicolon)  at  the  end  of  an  input-output
       declaration  makes  one  or several blank columns (up to 15) be printed in the result file
       after the input-output's value.

       The description block is a series of pattern description statements.  Each  pattern  is  a
       list of values preceded by a date and optionally by a label.
              [date] [label] : list_of_values ;

       Patterns statements should be ordered with stict growing dates in the series.

       The  date  may  be  either  an  absolute  date or a relative date.  An absolute date is an
       integer followed by a time unit.  A relative date is a '+' followed by an  integer  and  a
       time  unit  (the  reference  is  the  date of the previous pattern description statement).
       Legal time unit are ps, ns, us and ms.
              < 200 ps >,<4500ns>,< 12us > are legal absolute dates.  < +200  ps  >,<+4500ns>,<+1
              us> are legal relative dates.

       A  label  is  an  identifier (in VHDL syntax). The list_of_values is a set of values. Each
       value is associated with one input-output. The value of rank i  corresponds  to  the  i-th
       input-output. Depending on the format, legal values for inputs are:

       B (binary)
                 0 and, 1

       O (octal) 0, 1, 2, 3, 4, 5, 6 and, 7

       X (hexa.) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and, F

       For  each  output  the  user  can  predict  a  value.  This  bring the simulator to make a
       comparison between this value and the one calculated during the simulation.  Predicting  a
       ´*´  (star)  as an output value disables the comparison. Values must be preceeded by a ´?´
       (question mark). The ´?´ can be omitted when using a ´*´. Depending on the  format,  legal
       values for outputs are :

       B (binary)
                 0, 1 and *

       O (octal) 0, 1, 2, 3, 4, 5, 6, 7 and *

       X (hexa.) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F and *

       Using the binary format ´?1´ can be replaced by ´+´ (plus) and ´?0´ by ´-´ (minus).

       Example
                 in  A (0 to 15) X;
                 in  B (0 to 15) X;
                 in  Cin;
                 out Cout;
                 signal S (0 to 15) X;
                 register Accu.A (0 to 15) X;

                 begin

                 <   0 ns > pattern_0 : F0F0 0A0A 1 ?0 ?FAFA ?6DE7;
                 < +10 ns > pattern_1 : 0F0F F6F0 0  +  **** ?54FC;

                 end;

       Putting  one  or  several  additional ´;´ (semicolon) at the end of a pattern makes one or
       several blank lines (up to 15) be printed in the result file after the pattern.

       Other statements (called actions) such as changing registers value or saving the state  of
       the circuit can be placed in the description block.

       The  content  of  a  register  can  be  forced to a user defined value using the following
       statement:
              register_name <= value ;

       Register_name is a string representing the name of the register to be forced  (written  in
       the same form as described above).

       Value can be given in hexadecimal (X), octal (O) or binary (B) format :

       Examples  X"0FE46"
                 O"0345"
                 B"01010111"
                 "0111000"
                 ´0´

       The  value  of  the register will be forced to value just before the pattern following the
       statement is executed.

       The state of the circuit can be saved after all patterns are processed using:
              save;

       The save; statement must be placed just before the end; instruction.  When writing a  long
       sequence  of  patterns,  this feature can be used to split the sequence into several small
       sequences (with a save statement at the end of each sequence) (see asimut(1)).

       In pat format a comment begins with either a ´#´ (sharp) or a ´--´  (two  adjacent  minus)
       and  extends  up  to  the end of the line. A comment marked by a ´--´ is simply ignored. A
       comment maked by a ´#´ is kept at compile time and reproduced at the  same  place  in  the
       result file.

DIAGNOSTICS

       Pat does not make the difference between upper and lower case letters.

       When  the specified read-write format is O (octal) for an array input-output and the range
       of the input-output doesn´t match a multiple of 3, the most significant bits - 1 or 2 bits
       - of the value are ignored.

       When  the specified read-write format is X (hexadecimal) for an array input-output and the
       range of the input-output doesn´t match a multiple of 4, the most significant bits - 1,  2
       or 3 bits - of the value are ignored.

       A  comment  beginning  with  a ´#´ (sharp) placed after the end; statement causes a syntax
       error.

SEE ALSO

       asimut(1), genpat(1), libpat(3)