Provided by: alliance_5.0-20110203-4_i386 bug

NAME

       vasy VHDL RTL subset.

DESCRIPTION

       This  document  describes  the  VHDL  subset  accepted  by VASY for RTL
       descriptions.

       CONCURRENT STATEMENTS
       In an RTL architecture most of the concurrent statements are supported.

       Allowed concurrent statements are:
              block
              concurrent assertion
              process
              concurrent signal assignment
              component instantiation statement
       generate statement

       SEQUENTIAL STATEMENTS
       Inside a process, all sequential  statements  including  loops,  signal
       assignment, variable assignment are supported.

       TYPE
       All   types   usefull   for   synthesis  are  accepted  (IEEE-1164  and
       IEEE-1076.3), and all types defined in the VHDL  Alliance  subset  (see
       vbe(5) for more details).

       OPERATORS
       All  operators usefull  for synthesis are accepted, such as arithmetic,
       logical and relationnal operators   (IEEE-1164  and  IEEE-1076.3),  and
       those  defined  in  the  VHDL  Alliance  subset  (see  vbe(5)  for more
       details).

       HARDWARE DESCRIPTION EXAMPLES

       A MULTIPLEXER may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       entity mux is
       port(
         sel,a,b : in std_logic;
         mux_out : out std_logic );
       end mux;

       architecture rtl_1 of mux is
       begin
        process( sel,a,b )
        begin
          if (sel='1') then mux_out <= a;
                       else mux_out <= b;
          end if;
        end process;
       end rtl_1;

       architecture rtl_2 of mux is
       begin
         mux_out <= a when sel='1' else b;
       end rtl_2;

       A LATCH may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       entity latch is
       port(
         en,a : in std_logic;
         latch_out : out std_logic );
       end latch;

       architecture rtl_1 of latch is
       begin
        process( en, a )
        begin
          if (en='1') then latch_out <= a;
          end if;
        end process;
       end rtl_1;

       A D-FLIP-FLOP may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       entity d_ff is
       port(
          ck,a : in std_logic;
         d_ff_out : out std_logic );
       end d_ff;

       architecture rtl_1 of d_ff is
       begin
        process( ck )
        begin
          if (ck='1') then d_ff_out <= a;
          end if;
        end process;
       end rtl_1;

       architecture rtl_2 of d_ff is
       begin
        process( ck )
        begin
          if (ck='1' and ck'event)
          then d_ff_out <= a;
          end if;
        end process;
       end rtl_2;

       architecture rtl_3 of d_ff is
       begin
        process
        begin
          wait until ck='1';
          d_ff_out <= a;
        end process;
       end rtl_3;

       A TRISTATE BUFFER may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       entity trs is
       port(
          en,a : in std_logic;
          trs_out : out std_logic );
       end trs;

       architecture rtl_1 of trs is
       begin
        process( en,a )
        begin
          if (en='1') then trs_out <= a;
                      else trs_out <= 'Z';
          end if;
        end process;
       end rtl_1;

       architecture rtl_2 of d_ff is
       begin
        trs_out <= a when en='1' else 'Z';
       end rtl_2;

       A RAM may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       use IEEE.numeric_std.all;

       entity ram is
       port( clk,wr : in std_logic;
             adr : std_logic_vector(1 downto 0);
             i0  : in std_logic_vector(3 downto 0);
             o0  : out std_logic_vector(3 downto 0)
            );
       end ram;

       architecture rtl_1 of ram is
         type my_array is array (0 to 3) of std_logic_vector(3 downto 0);
         signal s : my_array;
       begin
        process
        begin
          wait until (clk='0' and clk'event);
          if (wr='1')
          then s(to_integer(unsigned(adr))) <= I0;
          end if;
        end process;
        o0 <= s(to_integer(unsigned(adr)));
       end rtl_1;

       A ROM may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       use IEEE.numeric_std.all;

       entity rom is
       port( adr : in  std_logic_vector(1 downto 0);
             o0  : out std_logic_vector(3 downto 0)
           );
       end rom;

       architecture rtl_1 of rom is
         subtype my_word is std_logic_vector(3 downto 0);
         type my_array is array (0 to 3) of my_word;
         constant s : my_array := ( "0000", "0001", "0010", "0011" );
       begin
         o0 <= s(to_integer(unsigned(adr)));
       end rtl_1;

       A PRIORITY DECODER may be described as follow:

       library IEEE;
       use IEEE.std_logic_1164.all;
       use IEEE.numeric_std.all;

       entity decod is
       port( A : in std_logic_vector(3 downto 0);
             B : out std_logic_vector(2 downto 0));
       end decod;
       architecture rtl_1 of decod is
       begin
        process( a )
        begin
          b <= "111";
          for i in a'range   -- Static For Loop are unrolled !
          loop
            exit when a(i)='1';
            b <= std_logic_vector(to_unsigned(i,3));
          end loop;
        end process;
       end rtl_1;

SEE ALSO

       vasy(1), vbe(5), vhdl(5), vst(5), boom(1), loon(1), boog(1), asimut(1),
       proof(1)