Provided by: llvm-3.4_3.4-1ubuntu3_amd64 
NAME
llvm-rtdyld - manual page for llvm-rtdyld 3.4
DESCRIPTION
OVERVIEW: llvm MC-JIT tool
USAGE: llvm-rtdyld [options] <input file>
OPTIONS:
-asm-verbose - Add comments to directives.
-bounds-checking-single-trap - Use one trap block per function
-cppfname=<function name> - Specify the name of the generated function
-cppfor=<string> - Specify the name of the thing to generate
-cppgen - Choose what kind of output to generate
=program
- Generate a complete program
=module
- Generate a module definition
=contents
- Generate contents of a module
=function
- Generate a function definition
=functions
- Generate all function definitions
=inline
- Generate an inline function
=variable
- Generate a variable definition
=type - Generate a type definition
-disable-debug-info-verifier -
-disable-spill-fusing - Disable fusing of spill code into instructions
-enable-correct-eh-support - Make the -lowerinvoke pass insert expensive, but
correct, EH code
-enable-load-pre -
-enable-objc-arc-opts - enable/disable all ARC Optimizations
-enable-tbaa -
-entry=<string> - Function to call as entry point.
Action to perform:
-execute - Load, link, and execute the inputs.
-printline - Load, link, and print line information for each
function.
-fatal-assembler-warnings - Consider warnings as error
-fdata-sections - Emit data into separate sections
-ffunction-sections - Emit functions into separate sections
-help - Display available options (-help-hidden for
more)
-internalize-public-api-file=<filename> - A file containing list of symbol names to
preserve
-internalize-public-api-list=<list> - A list of symbol names to preserve
-join-liveintervals - Coalesce copies (default=true)
-limit-float-precision=<uint> - Generate low-precision inline sequences for some
float libcalls
-mc-x86-disable-arith-relaxation - Disable relaxation of arithmetic instruction for
X86
-mips16-hard-float - MIPS: mips16 hard float enable.
-mno-ldc1-sdc1 - Expand double precision loads and stores to
their single precision counterparts
-nvptx-sched4reg - NVPTX Specific: schedule for register pressue
-pre-RA-sched - Instruction schedulers available (before
register allocation):
=vliw-td
- VLIW scheduler
=list-ilp
- Bottom-up register pressure aware list scheduling which tries to balance ILP
and register pressure
=list-hybrid
- Bottom-up register pressure aware list scheduling which tries to balance
latency and register pressure
=source
- Similar to list-burr but schedules in source order when possible
=list-burr
- Bottom-up register reduction list scheduling
=linearize
- Linearize DAG, no scheduling
=fast - Fast suboptimal list scheduling
=default
- Best scheduler for the target
-print-after-all - Print IR after each pass
-print-before-all - Print IR before each pass
-print-machineinstrs=<pass-name> - Print machine instrs
-regalloc - Register allocator to use
=default
- pick register allocator based on -O option
=basic - basic register allocator
=fast - fast register allocator
=greedy
- greedy register allocator
=pbqp - PBQP register allocator
-spiller - Spiller to use: (default: standard)
=trivial
- trivial spiller
=inline
- inline spiller
-stats - Enable statistics output from program (available
with Asserts)
-time-passes - Time each pass, printing elapsed time for each
on exit
-verify-dom-info - Verify dominator info (time consuming)
-verify-loop-info - Verify loop info (time consuming)
-verify-regalloc - Verify during register allocation
-verify-region-info - Verify region info (time consuming)
-verify-scev - Verify ScalarEvolution's backedge taken counts
(slow)
-version - Display the version of this program
-x86-asm-syntax - Choose style of code to emit from X86 backend:
=att - Emit AT&T-style assembly
=intel - Emit Intel-style assembly
SEE ALSO
The full documentation for llvm-rtdyld is maintained as a Texinfo manual. If the info and
llvm-rtdyld programs are properly installed at your site, the command
info llvm-rtdyld
should give you access to the complete manual.