Provided by: freebsd-manpages_10.1~RC1-1_all
terasic_mtl — driver for the Terasic/Cambridge Multi-Touch LCD device
device terasic_mtl In /boot/device.hints: hint.terasic_mtl.0.at="nexus0" hint.terasic_mtl.0.reg_maddr=0x70400000 hint.terasic_mtl.0.reg_msize=0x1000 hint.terasic_mtl.0.pixel_maddr=0x70000000 hint.terasic_mtl.0.pixel_msize=0x177000 hint.terasic_mtl.0.text_maddr=0x70177000 hint.terasic_mtl.0.text_msize=0x2000
The terasic_mtl device driver provides support for the Terasic Multi-Touch LCD combined as controlled by a University of Cambridge's IP Core. Three device nodes are instantiated, representing various services supported by the device: terasic_regX Memory-mapped register interface, including touch screen input. terasic_pixelX Memory-mapped pixel-oriented frame buffer. terasic_textX Memory-mapped text-oriented frame buffer. terasic_mtl devices are also attached to the syscons(4) framework, which implements a VT- compatible terminal connected to the tty(4) framework. ttyvX device nodes may be added to ttys(5) in order to launch login(1) sessions at boot. Register, text, and pixel devices may be accessed using read(2) and write(2) system calls, and also memory mapped using mmap(2).
The terasic_mtl device driver first appeared in FreeBSD 10.0.
The terasic_mtl device driver and this manual page were developed by SRI International and the University of Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) (“CTSRD”), as part of the DARPA CRASH research programme. This device driver was written by Robert N. M. Watson.
The syscons(4) attachment does not support the hardware cursor feature. A more structured interface to control registers using the ioctl(2) system call, would sometimes be preferable to memory mapping. For touch screen input, it would be highly desirable to offer a streaming interface whose events can be managed using poll(2) and related system calls, with the kernel performing polling rather than the userspace application. terasic_mtl supports only a nexus bus attachment, which is appropriate for system-on-chip busses such as Altera's Avalon bus. If the IP core is configured off of another bus type, then additional bus attachments will be required.