bionic (5) sxlib.5.gz

Provided by: alliance_5.1.1-1.1build1_amd64 bug

NAME

       sxlib - a portable CMOS Standard Cell Library

DESCRIPTION

       sxlib  library  contains standard cells that have been developed at UPMC-ASIM/LIP6. This manual gives the
       list of available cells, with their behavior, width, maximum delay and input fan-in.  This  manual  gives
       also  few thumb rules to help the user to well use the cells. The given delay are the maximum (that means
       worst case for a generic .35 micron process).  More precise delay can be found in ALLIANCE VHDL  behavior
       files (.vbe file).  Cell-name is built that way <behavior>_<output drive> (see explanations below).

       Four files are attached to each cell:-
       - ALLIANCE Layout ............... cell-name.ap
       - ALLIANCE Transistor net-list .. cell-name.al
       - ALLIANCE VHDL behavior ........ cell-name.vbe
       - Compiled HILO behavior ........ 0000000xx.dat

       And few files more:-
       - CATAL ......................... ALLIANCE catalog file
       - sxlib.cct ..................... Cell definition for HILO CAD tools
       - CIRCUIT.idx ................... HILO catalog file
       - sxlib.lib ..................... Cell definition for Synopsys CAD tools
       - sxlib.db ...................... Compiled cell definition for Synopsys
       - sxlib.sdb ..................... Icon definition for Synopys

PHYSICAL OUTLINE

       sxlib  uses  the  symbolic  layout  promoted  by  Alliance  in order to provide process independence. All
       dimensions are in lambda units. The mapping to a specific process CIF or GDS2 layout must be performed by
       the s2r tool (symbolic to real), which uses a value for the lambda (e.g. 1 lambda=0.3um).

              _________________
          50 |       VDD       |
          45 |_________________|     x : place of virtual connector.
          40 |           x     |
          35 |        x  x     |         they are named : name_<y>
          30 |  x     x        |
          25 |  x     x        |         for example : i0_20
          20 |  x              |                       i0_25
          15 |           x     |                       i0_30
          10 |_________________|
           5 |       VSS       |
           0 |_________________|
             0  5 10 15 20 25 30

       All  cells  are 50 lambdas high and N times 5 lambdas wide, where N is the number of pitches. That is the
       only physical information given in the cell list below.  Power supplies are in horizontal ALU1 and are  6
       lambdas  wide.   Connectors  are  inside the cells, placed on a 5x5 grid.  Half layout design rules are a
       warranty for any layer on any face, except for the power supply and NWELL.  Cells can be abutted  in  all
       directions whenever the supply is well connected and connectors are always placed on the 5x5 grid.

DELAY MODEL

       Cells  have  been  extracted  and  simulated by using a generic 0.35um process in order to give realistic
       values for the delays and capacitances.  We chose to give only the worst delay for  each  output  signal,
       though  it  is  not very realistic (since delay depends on each input, an input can be easily up to twice
       faster than another). However, we just wanted to give an idea of the relative delay.

       Furthermore, we added 0.6ns to each output delay in order to take into  account  the  delay  due  to  the
       signal  commutation.  We  have  supposed the output drives the maximum capacitance. This capacitance have
       been computed as follow. We considered that a good slope signal for this  process  was  0.8ns.   Then  we
       searched  for  the capacitance required to obtain the same input and output slope (0.8ns) for the smaller
       inverter (inv_x1). That was 125fF. We simulated the same inverter without output capacitance.  The  delay
       difference  was  about  0.6ns.  This  result  is  not exactly the same for all cells, but 0.6ns is a good
       approximation.

       The given delay is then a worst case (70degree, 2.7Volt, slow process,  worst  input),  an  idea  of  the
       typical  delay  can  be  obtain  by  dividing  worst delay by 1.5, and best delay by dividing by 2.  More
       detailed data can be found in GENERIC data included in the VHDL files (.vbe). Examples can  be  found  at
       the end of this manual.

       At  last, to get a very better idea about the real delay without simulating the spice transistor netlist,
       it is required to use the TAS (1) tool, which is a timing static analyzer able to give the longer and the
       shorter path for a given process.

OUTPUT DRIVE

       The  output  drive of a cell gives an information on the faculty for the cell to drive a big capacitance.
       This faculty depends on the rising and falling output resistance. The smaller the resistance, the  bigger
       can  be  the  capacitance.   Minimum  drive  is  x1.  This corresponds to the smallest available inverter
       (inv_x1). x2 means the cell is equivalent (from the driving point of view) at two  smaller  inverters  in
       parallel, and so on.

       The  maximum  output  drive  is  x8.  It  is  limited because of the maximum output slope and the maximum
       authorized instantaneous current. If it was bigger the output slope could be very tight and  the  current
       too big.

       With the 0.35um process, an x1 is able to drive about 125fF, x2 -> 250fF, x4 -> 500fF,x8 -> 1000fF.  This
       is just an indication since if a cell is overloaded, the only consequence is to increase the  propagation
       time.  On  the  other  hand,  it  is  not  very  good to under-load a cell because this leads to a signal
       overshoot.  Actually, for big gate, such as noa3ao322_x1, x1 means  maximal  driving  strength  reachable
       with  a  single  logic  layer,  that  can be much less than an inv_x1. That is why is the cell list below
       contains more precise drive strengh. As you can see noa3ao322_x1 as a output drive strengh of  0.6,  that
       means 0.6 time an inverter, so say it can drive about 0.6*125fF=75fF.

       With  the  0.35um  process, a 1 lambda interconnect wire is about 0.15fF, an average cell fan-in is 10fF.
       Then, if it needs about 50 lambdas to connect 2 cells, an  x1  cell  is  able  to  drive  about  7  cells
       (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas only 2 cells. Note that 50 lambdas means
       cells are very close one from each other, nearly abutted, 100 lambdas is an average value.

       All this are indications.  Only a timing analysis on the extracted transistor net-list  from  layout  can
       tell if a cell is well used or not (see tas(1) for informations about static timing analysis).

BEHAVIOR

       For  most  of  cells,  the  user  can  deduce  the  cell behavior just by reading its name.  That is very
       intuitive for inverter and more complex for and/or cells.  For the last, the name gives the  and/or  tree
       structure.  The input order for the VHDL interface component is always the alphabetic order.

       inv           : inversor buffer
       buf           : buffer
       [n]ts         : [not] tree-state
       [n]xr<i>      : [not] xor <i> inputs
       [n]mx<i>      : [not] multiplexor <i> inputs with coded command
       [n][sd]ff<i>  : [not] [static|dynamic] flip-flop <i> inputs
       [n]oa...      : [not] and/or function (see below)

       and_or cell (YACC (1) grammar):-

       NAME     : n OA_CELL                 -> not OA_CELL
                | OA_CELL                   -> OA_CELL

       OA_CELL  : OPERATOR INPUTS           -> function with INPUTS inputs
                | OPERATOR OA_CELLS INPUTS  -> function with INPUTS inputs
                                               where some inputs are OA_CELL

       OPERATOR : a                         -> and
                | o                         -> or
                | n                         -> not

       OA_CELLS : OA_CELLS OA_CELL          -> list of OA_CELL
                | OA_CELL                   -> last OA_CELL of the list

       INPUTS   : integer                   -> number of inputs

       The input names are implicit and formed that way i<number>.
       They are attributed in order beginning by i0.

       nx where x is a number means there are x inverters in parallel. For
       example an23 is an and with 3 inputs of which two are inverted, that
       is and( not(i0), not(i1), i2).

       Examples:- (some are not in sxlib)

       na2       : not( and(i0,i1))
       on12      : or( not(i0), i1)
       noa2a22   : not( or( and(i0,i1), and(i2,i3)))
       noa23     : not( or( and(i0,i1), i3))
       noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))

       Note that xr2 could not be expressed with an and/or formulea even if
       xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122
       but the input names are not well distributed.

CELL LIST

       All available cells are listed below. The first column is the pitch width.  The pitch value is 5 lambdas.
       The height is 50. Area is then <number>*5*50.

       The second column is the output drive strenght compared  with  the  inv_x1  output  drive  strenght  (see
       explanation above in section OUTPUT DRIVE).

       The  following  column  is  the  delay  in  nano-seconds.   Remember this delay corresponds to the slower
       input+0.6ns (see explanation above in section DELAY MODEL).

       The last column gives the function behavior with input capacitance.  / means not, + means  or,  .   means
       and,  ^  means  xor.   Each  input  is  followed  by  fan-in capacitance in fF, (e.g. i0<11> means i0 pin
       capacitance is 11fF).

       For some cells, such as fulladder, it was not possible to internally  connect  all  inputs.   That  means
       there  are  several  inputs  that  must be externally connected.  In the following list, these inputs are
       followed by a star (*) character in the equation.

       For example, fulladder equation is sout <= (a* . b* . cin*).  a* replaces a0, a1, a2,  a3  that  must  be
       explicitly  connected by the user.  Note also few cells have more than one output. In that case there are
       several lines in the list, one by output.
       =================================================================
       WIDTH NAME  DRIVE DELAY BEHAVIOR with cin
       -------------------------------------------------------- INVERSOR
        3 inv_x1       1.0 0.7  nq <= /i<8>
        3 inv_x2       1.6 0.7  nq <= /i<12>
        4 inv_x4       3.6 0.7  nq <= /i<26>
        7 inv_x8       8.4 0.7  nq <= /i<54>
       ---------------------------------------------------------- BUFFER
        4 buf_x2       2.1 1.0   q <=  i<6>
        5 buf_x4       4.3 1.0   q <=  i<9>
        8 buf_x8       8.4 1.0   q <=  i<15>
       ------------------------------------------------------ THREE STATE
        6 nts_x1       1.2 0.8  IF (cmd<14>) nq <= /i<14>
        8 nts_x2       2.4 0.9  IF (cmd<18>) nq <= /i<28>
       10 ts_x4        4.3 1.1  IF (cmd<19>)  q <= i<8>
       13 ts_x8        8.4 1.2  IF (cmd<19>)  q <= i<8>
       -------------------------------------------------------------- AND
        4 na2_x1       1.0 0.9  nq <= /(i0<11>.i1<11>)
        7 na2_x4       4.3 1.2  nq <= /(i0<10>.i1<10>)
        5 na3_x1       0.9 1.0  nq <= /(i0<11>.i1<11>.i2<11>)
        8 na3_x4       4.3 1.3  nq <= /(i0<10>.i1<10>.i2<10>)
        6 na4_x1       0.7 1.0  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
       10 na4_x4       4.3 1.4  nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
        5 a2_x2        2.1 1.0   q <=  (i0<9>.i1<11>)
        6 a2_x4        4.3 1.1   q <=  (i0<9>.i1<11>)
        6 a3_x2        2.1 1.1   q <=  (i0<10>.i1<10>.i2<10>)
        7 a3_x4        4.3 1.2   q <=  (i0<10>.i1<10>.i2<10>)
        7 a4_x2        2.1 1.2   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
        8 a4_x4        4.3 1.3   q <=  (i0<10>.i1<10>.i2<10>.i3<10>)
        5 an12_x1      1.0 1.0   q <=  (/i0<12>).i1<9>
        8 an12_x4      4.3 1.1   q <=  (/i0<9>).i1<11>
       --------------------------------------------------------------- OR
        4 no2_x1       1.0 0.9  nq <= /(i0<12>+i1<12>)
        8 no2_x4       4.3 1.2  nq <= /(i0<12>+i1<11>)
        5 no3_x1       0.8 1.0  nq <= /(i0<12>+i1<12>+i2<12>)
        8 no3_x4       4.3 1.3  nq <= /(i0<12>+i1<12>+i2<11>)
        6 no4_x1       0.6 1.1  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
       10 no4_x4       4.3 1.4  nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
        5 o2_x2        2.1 1.0   q <=  (i0<10>+i1<10>)
        6 o2_x4        4.3 1.1   q <=  (i0<10>+i1<10>)
        6 o3_x2        2.1 1.1   q <=  (i0<10>+i1<10>+i2<9>)
       10 o3_x4        4.3 1.2   q <=  (i0<10>+i1<10>+i2<9>)
        7 o4_x2        2.1 1.2   q <=  (i0<10>+i1<10>+i2<10>+i3<9>)
        8 o4_x4        4.3 1.3   q <=  (i0<12>+i1<12>+i2<12>+i3<12>)
        5 on12_x1      1.0 0.9   q <=  (/i0<11>)+i1<9>
        8 on12_x4      4.3 1.1   q <=  (/i0<9>)+i1<10>
       --------------------------------------------------------- AND/OR 3
        6 nao22_x1     1.2 0.9  nq <= /((i0<14>+i1<14>).i2<14>)
       10 nao22_x4     4.3 1.3  nq <= /((i0<8> +i1<8>) .i2<9>)
        6 noa22_x1     1.2 0.9  nq <= /((i0<14>.i1<14>)+i2<14>)
       10 noa22_x4     4.3 1.3  nq <= /((i0<8> .i1<8>) +i2<9>)
        6 ao22_x2      2.1 1.2   q <=  ((i0<8>+i1<8>).i2<9>)
        8 ao22_x4      4.3 1.3   q <=  ((i0<8>+i1<8>).i2<9>)
        6 oa22_x2      2.1 1.2   q <=  ((i0<8>.i1<8>)+i2<9>)
        8 oa22_x4      4.3 1.3   q <=  ((i0<8>.i1<8>)+i2<9>)
       --------------------------------------------------------- AND/OR 4
        7 nao2o22_x1   1.2 1.0  nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
       11 nao2o22_x4   4.3 1.4  nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
        7 noa2a22_x1   1.2 1.0  nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
       11 noa2a22_x4   4.3 1.4  nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
        9 ao2o22_x2    2.1 1.2   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
       10 ao2o22_x4    4.3 1.3   q <=  ((i0<8>+i1<8>).(i2<8>+i3<8>))
        9 oa2a22_x2    2.1 1.2   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
       10 oa2a22_x4    4.3 1.4   q <=  ((i0<8>.i1<8>)+(i2<8>.i3<8>))
       --------------------------------------------------------- AND/OR 5
        7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
       11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
       10 oa2ao222_x2  2.1 1.2  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
       11 oa2ao222_x4  4.3 1.3  q <=  ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
       --------------------------------------------------------- AND/OR 6
       10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
                                      +(i4<14>.i5<14>))
       13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
                                      +(i4<14>.i5<14>))
       12 oa2a2a23_x2  2.1 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
                                      +(i4<14>.i5<14>))
       13 oa2a2a23_x4  4.3 1.4  q <=  ((i0<13>.i1<14>) +(i2<14>.i3<14>)
                                      +(i4<14>.i5<14>))
       --------------------------------------------------------- AND/OR 7
        9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>)
                                      +((i3<13>+i4<13>+i5<13>).i6<13>))
       11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>)
                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
       10 oa3ao322_x2  2.1 1.2  q <= /((i0<10>.i1<9>.i2<9>)
                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
       11 oa3ao322_x4  4.3 1.3  q <= /((i0<10>.i1<9>.i2<9>)
                                      +((i3<9>+i4<9>+i5<9>).i6<9>))
       --------------------------------------------------------- AND/OR 8
       14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>)
                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
       17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>)
                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
       15 oa2a2a2a24_x2  2.1 1.5  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
       16 oa2a2a2a24_x4  4.3 1.6  q <=  ((i0<14>.i1<14>)+(i2<14>.i3<13>)
                                        +(i4<13>.i5<13>)+(i6<14>.i7<14>))
       ------------------------------------------------------ MULTIPLEXER
        7 nmx2_x1      1.2 1.0  nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
       12 nmx2_x4      4.3 1.3  nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
        9 mx2_x2       2.1 1.1   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
       10 mx2_x4       4.3 1.3   q <=   (i0<8>./cmd<17>)+(i1<9>.cmd)
       12 nmx3_x1      0.4 1.2  nq <= /((i0<9>./cmd0<15>)
                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
       15 nmx3_x4      4.3 1.7  nq <= /((i0<9>./cmd0<15>)
                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
       13 mx3_x2       2.1 1.4   q <=  ((i0<9>./cmd0<15>)
                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
       14 mx3_x4       4.3 1.6   q <=  ((i0<9>./cmd0<15>)
                                       +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
       -------------------------------------------------------------- XOR
        9 nxr2_x1      1.2 1.1  nq <= /(i0<21>^i1<22>)
       11 nxr2_x4      4.3 1.2  nq <= /(i0<20>^i1<21>)
        9 xr2_x1       1.2 1.0   q <=  (i0<21>^i1<22>)
       12 xr2_x4       4.3 1.2   q <=  (i0<20>^i1<21>)
       -------------------------------------------------------- FLIP-FLOP
                                   nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
       18 sff1_x4      4.3 1.7  IF RISE(ck<8>)
                                    q <= i<8>
       24 sff2_x4      4.3 1.9  IF RISE(ck<8>)
                                    q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
       28 sff3_x4      4.3 2.4  IF RISE(ck<8>)
                                    q <= (i0<9>./cmd0<15>)
                                        +(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
       ------------------------------------------------------------ ADDER
       16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>)
                       2.1 1.0 cout <= (a.b)
       18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>)
                       4.3 1.1 cout <= (a.b)
       20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>)
                       2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*)
       21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>)
                       4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*)
       ---------------------------------------------------------- SPECIAL
        3 zero_x0       0   0  nq <= '0'
        3 one_x0        0   0   q <= '1'
        2 tie_x0        0   0  Body tie cell
        1 rowend_x0     0   0  Empty cell
       ==================================================================

NEW CELLS

       It is possible to add new cells in the library just by providing the 3 files .ap, .al  and  .vbe  in  the
       standard  cell  directory.   The layout view can be created with the symbolic editor graal.  The physical
       outline is given above.  The net-list view can be automatically generated with the lynx  extractor.   The
       behavioral  view  must  be written by the designer and checked with the yagle functional abstractor.  The
       file must contain the generic fields in order to be used by  the  logic  synthesis  tools  and  the  I/Os
       terminals must be in the same order (alphabetic) in the .vbe and .al files.

       If you develop new cells, please send the corresponding files to alliance-users@asim.lip6.fr

VHDL FILES

       You can find below the commented VHDL GENERIC for the na2_x4 cell.
       ENTITY na2_x4 IS
       GENERIC (
         CONSTANT area          : NATURAL := 1750; -- lamba * lambda
         CONSTANT transistors   : NATURAL := 10;   -- number of
         CONSTANT cin_i0        : NATURAL := 10;   -- femto Farad for i0
         CONSTANT cin_i1        : NATURAL := 10;   -- femto Farad for i1
         CONSTANT tplh_i1_nq    : NATURAL := 606;  -- propag. time in pico-sec
                                                   -- from i1 falling
                                                   -- to   nq rizing
         CONSTANT rup_i1_nq     : NATURAL := 890;  -- resitance in Ohms when nq
                                                   -- rizing due to i1 change
         CONSTANT tphl_i1_nq    : NATURAL := 349;  -- propag time when nq falls
         CONSTANT rdown_i1_nq   : NATURAL := 800;  -- resist when nq falls
         CONSTANT tplh_i0_nq    : NATURAL := 557;  -- idem for i0
         CONSTANT rup_i0_nq     : NATURAL := 890;
         CONSTANT tphl_i0_nq    : NATURAL := 408;
         CONSTANT rdown_i0_nq   : NATURAL := 800
       );
       PORT (
         i0     : in  BIT;
         i1     : in  BIT;
         nq     : out BIT;
         vdd    : in  BIT;
         vss    : in  BIT
       );

SEE ALSO

       MBK_CATA_LIB  (1),  catal(1),  ocp(1),  nero(1),  cougar(1), boom(1), loon(1), boog(1), genlib(1), ap(5),
       al(5), vbe(5)