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Data types used by CUDA Runtime


#define CUDA_EGL_MAX_PLANES 3
#define CUDA_IPC_HANDLE_SIZE 64
#define cudaArrayColorAttachment 0x20
#define cudaArrayCubemap 0x04
#define cudaArrayDefault 0x00
#define cudaArrayLayered 0x01
#define cudaArraySurfaceLoadStore 0x02
#define cudaArrayTextureGather 0x08
#define cudaCooperativeLaunchMultiDeviceNoPostSync 0x02
#define cudaCooperativeLaunchMultiDeviceNoPreSync 0x01
#define cudaCpuDeviceId ((int)-1)
#define cudaDeviceBlockingSync 0x04
#define cudaDeviceLmemResizeToMax 0x10
#define cudaDeviceMapHost 0x08
#define cudaDeviceMask 0x1f
#define cudaDevicePropDontCare
#define cudaDeviceScheduleAuto 0x00
#define cudaDeviceScheduleBlockingSync 0x04
#define cudaDeviceScheduleMask 0x07
#define cudaDeviceScheduleSpin 0x01
#define cudaDeviceScheduleYield 0x02
#define cudaEventBlockingSync 0x01
#define cudaEventDefault 0x00
#define cudaEventDisableTiming 0x02
#define cudaEventInterprocess 0x04
#define cudaExternalMemoryDedicated 0x1
#define cudaHostAllocDefault 0x00
#define cudaHostAllocMapped 0x02
#define cudaHostAllocPortable 0x01
#define cudaHostAllocWriteCombined 0x04
#define cudaHostRegisterDefault 0x00
#define cudaHostRegisterIoMemory 0x04
#define cudaHostRegisterMapped 0x02
#define cudaHostRegisterPortable 0x01
#define cudaInvalidDeviceId ((int)-2)
#define cudaIpcMemLazyEnablePeerAccess 0x01
#define cudaMemAttachGlobal 0x01
#define cudaMemAttachHost 0x02
#define cudaMemAttachSingle 0x04
#define cudaOccupancyDefault 0x00
#define cudaOccupancyDisableCachingOverride 0x01
#define cudaPeerAccessDefault 0x00
#define cudaStreamDefault 0x00
#define cudaStreamLegacy ((cudaStream_t)0x1)
#define cudaStreamNonBlocking 0x01
#define cudaStreamPerThread ((cudaStream_t)0x2)


typedef struct cudaArray * cudaArray_const_t
typedef struct cudaArray * cudaArray_t
typedef struct CUeglStreamConnection_st * cudaEglStreamConnection
typedef enum cudaError cudaError_t
typedef struct CUevent_st * cudaEvent_t
typedef struct CUexternalMemory_st * cudaExternalMemory_t
typedef struct CUexternalSemaphore_st * cudaExternalSemaphore_t
typedef struct CUgraph_st * cudaGraph_t
typedef struct CUgraphExec_st * cudaGraphExec_t
typedef struct cudaGraphicsResource * cudaGraphicsResource_t
typedef struct CUgraphNode_st * cudaGraphNode_t
typedef void(CUDART_CB * cudaHostFn_t )(void *userData)
typedef struct cudaMipmappedArray * cudaMipmappedArray_const_t
typedef struct cudaMipmappedArray * cudaMipmappedArray_t
typedef enum cudaOutputMode cudaOutputMode_t
typedef struct CUstream_st * cudaStream_t
typedef unsigned long long cudaSurfaceObject_t
typedef unsigned long long cudaTextureObject_t


enum cudaCGScope { cudaCGScopeInvalid = 0, cudaCGScopeGrid = 1, cudaCGScopeMultiGrid = 2 }
enum cudaChannelFormatKind { cudaChannelFormatKindSigned = 0, cudaChannelFormatKindUnsigned = 1, cudaChannelFormatKindFloat = 2, cudaChannelFormatKindNone = 3 }
enum cudaComputeMode { cudaComputeModeDefault = 0, cudaComputeModeExclusive = 1, cudaComputeModeProhibited = 2, cudaComputeModeExclusiveProcess = 3 }
enum cudaDeviceAttr { cudaDevAttrMaxThreadsPerBlock = 1, cudaDevAttrMaxBlockDimX = 2, cudaDevAttrMaxBlockDimY = 3, cudaDevAttrMaxBlockDimZ = 4, cudaDevAttrMaxGridDimX = 5, cudaDevAttrMaxGridDimY = 6, cudaDevAttrMaxGridDimZ = 7, cudaDevAttrMaxSharedMemoryPerBlock = 8, cudaDevAttrTotalConstantMemory = 9, cudaDevAttrWarpSize = 10, cudaDevAttrMaxPitch = 11, cudaDevAttrMaxRegistersPerBlock = 12, cudaDevAttrClockRate = 13, cudaDevAttrTextureAlignment = 14, cudaDevAttrGpuOverlap = 15, cudaDevAttrMultiProcessorCount = 16, cudaDevAttrKernelExecTimeout = 17, cudaDevAttrIntegrated = 18, cudaDevAttrCanMapHostMemory = 19, cudaDevAttrComputeMode = 20, cudaDevAttrMaxTexture1DWidth = 21, cudaDevAttrMaxTexture2DWidth = 22, cudaDevAttrMaxTexture2DHeight = 23, cudaDevAttrMaxTexture3DWidth = 24, cudaDevAttrMaxTexture3DHeight = 25, cudaDevAttrMaxTexture3DDepth = 26, cudaDevAttrMaxTexture2DLayeredWidth = 27, cudaDevAttrMaxTexture2DLayeredHeight = 28, cudaDevAttrMaxTexture2DLayeredLayers = 29, cudaDevAttrSurfaceAlignment = 30, cudaDevAttrConcurrentKernels = 31, cudaDevAttrEccEnabled = 32, cudaDevAttrPciBusId = 33, cudaDevAttrPciDeviceId = 34, cudaDevAttrTccDriver = 35, cudaDevAttrMemoryClockRate = 36, cudaDevAttrGlobalMemoryBusWidth = 37, cudaDevAttrL2CacheSize = 38, cudaDevAttrMaxThreadsPerMultiProcessor = 39, cudaDevAttrAsyncEngineCount = 40, cudaDevAttrUnifiedAddressing = 41, cudaDevAttrMaxTexture1DLayeredWidth = 42, cudaDevAttrMaxTexture1DLayeredLayers = 43, cudaDevAttrMaxTexture2DGatherWidth = 45, cudaDevAttrMaxTexture2DGatherHeight = 46, cudaDevAttrMaxTexture3DWidthAlt = 47, cudaDevAttrMaxTexture3DHeightAlt = 48, cudaDevAttrMaxTexture3DDepthAlt = 49, cudaDevAttrPciDomainId = 50, cudaDevAttrTexturePitchAlignment = 51, cudaDevAttrMaxTextureCubemapWidth = 52, cudaDevAttrMaxTextureCubemapLayeredWidth = 53, cudaDevAttrMaxTextureCubemapLayeredLayers = 54, cudaDevAttrMaxSurface1DWidth = 55, cudaDevAttrMaxSurface2DWidth = 56, cudaDevAttrMaxSurface2DHeight = 57, cudaDevAttrMaxSurface3DWidth = 58, cudaDevAttrMaxSurface3DHeight = 59, cudaDevAttrMaxSurface3DDepth = 60, cudaDevAttrMaxSurface1DLayeredWidth = 61, cudaDevAttrMaxSurface1DLayeredLayers = 62, cudaDevAttrMaxSurface2DLayeredWidth = 63, cudaDevAttrMaxSurface2DLayeredHeight = 64, cudaDevAttrMaxSurface2DLayeredLayers = 65, cudaDevAttrMaxSurfaceCubemapWidth = 66, cudaDevAttrMaxSurfaceCubemapLayeredWidth = 67, cudaDevAttrMaxSurfaceCubemapLayeredLayers = 68, cudaDevAttrMaxTexture1DLinearWidth = 69, cudaDevAttrMaxTexture2DLinearWidth = 70, cudaDevAttrMaxTexture2DLinearHeight = 71, cudaDevAttrMaxTexture2DLinearPitch = 72, cudaDevAttrMaxTexture2DMipmappedWidth = 73, cudaDevAttrMaxTexture2DMipmappedHeight = 74, cudaDevAttrComputeCapabilityMajor = 75, cudaDevAttrComputeCapabilityMinor = 76, cudaDevAttrMaxTexture1DMipmappedWidth = 77, cudaDevAttrStreamPrioritiesSupported = 78, cudaDevAttrGlobalL1CacheSupported = 79, cudaDevAttrLocalL1CacheSupported = 80, cudaDevAttrMaxSharedMemoryPerMultiprocessor = 81, cudaDevAttrMaxRegistersPerMultiprocessor = 82, cudaDevAttrManagedMemory = 83, cudaDevAttrIsMultiGpuBoard = 84, cudaDevAttrMultiGpuBoardGroupID = 85, cudaDevAttrHostNativeAtomicSupported = 86, cudaDevAttrSingleToDoublePrecisionPerfRatio = 87, cudaDevAttrPageableMemoryAccess = 88, cudaDevAttrConcurrentManagedAccess = 89, cudaDevAttrComputePreemptionSupported = 90, cudaDevAttrCanUseHostPointerForRegisteredMem = 91, cudaDevAttrCooperativeLaunch = 95, cudaDevAttrCooperativeMultiDeviceLaunch = 96, cudaDevAttrMaxSharedMemoryPerBlockOptin = 97, cudaDevAttrCanFlushRemoteWrites = 98, cudaDevAttrHostRegisterSupported = 99, cudaDevAttrPageableMemoryAccessUsesHostPageTables = 100, cudaDevAttrDirectManagedMemAccessFromHost = 101 }
enum cudaDeviceP2PAttr { cudaDevP2PAttrPerformanceRank = 1, cudaDevP2PAttrAccessSupported = 2, cudaDevP2PAttrNativeAtomicSupported = 3, cudaDevP2PAttrCudaArrayAccessSupported = 4 }
enum cudaEglColorFormat { cudaEglColorFormatYUV420Planar = 0, cudaEglColorFormatYUV420SemiPlanar = 1, cudaEglColorFormatYUV422Planar = 2, cudaEglColorFormatYUV422SemiPlanar = 3, cudaEglColorFormatRGB = 4, cudaEglColorFormatBGR = 5, cudaEglColorFormatARGB = 6, cudaEglColorFormatRGBA = 7, cudaEglColorFormatL = 8, cudaEglColorFormatR = 9, cudaEglColorFormatYUV444Planar = 10, cudaEglColorFormatYUV444SemiPlanar = 11, cudaEglColorFormatYUYV422 = 12, cudaEglColorFormatUYVY422 = 13, cudaEglColorFormatABGR = 14, cudaEglColorFormatBGRA = 15, cudaEglColorFormatA = 16, cudaEglColorFormatRG = 17, cudaEglColorFormatAYUV = 18, cudaEglColorFormatYVU444SemiPlanar = 19, cudaEglColorFormatYVU422SemiPlanar = 20, cudaEglColorFormatYVU420SemiPlanar = 21, cudaEglColorFormatY10V10U10_444SemiPlanar = 22, cudaEglColorFormatY10V10U10_420SemiPlanar = 23, cudaEglColorFormatY12V12U12_444SemiPlanar = 24, cudaEglColorFormatY12V12U12_420SemiPlanar = 25, cudaEglColorFormatVYUY_ER = 26, cudaEglColorFormatUYVY_ER = 27, cudaEglColorFormatYUYV_ER = 28, cudaEglColorFormatYVYU_ER = 29, cudaEglColorFormatYUV_ER = 30, cudaEglColorFormatYUVA_ER = 31, cudaEglColorFormatAYUV_ER = 32, cudaEglColorFormatYUV444Planar_ER = 33, cudaEglColorFormatYUV422Planar_ER = 34, cudaEglColorFormatYUV420Planar_ER = 35, cudaEglColorFormatYUV444SemiPlanar_ER = 36, cudaEglColorFormatYUV422SemiPlanar_ER = 37, cudaEglColorFormatYUV420SemiPlanar_ER = 38, cudaEglColorFormatYVU444Planar_ER = 39, cudaEglColorFormatYVU422Planar_ER = 40, cudaEglColorFormatYVU420Planar_ER = 41, cudaEglColorFormatYVU444SemiPlanar_ER = 42, cudaEglColorFormatYVU422SemiPlanar_ER = 43, cudaEglColorFormatYVU420SemiPlanar_ER = 44, cudaEglColorFormatBayerRGGB = 45, cudaEglColorFormatBayerBGGR = 46, cudaEglColorFormatBayerGRBG = 47, cudaEglColorFormatBayerGBRG = 48, cudaEglColorFormatBayer10RGGB = 49, cudaEglColorFormatBayer10BGGR = 50, cudaEglColorFormatBayer10GRBG = 51, cudaEglColorFormatBayer10GBRG = 52, cudaEglColorFormatBayer12RGGB = 53, cudaEglColorFormatBayer12BGGR = 54, cudaEglColorFormatBayer12GRBG = 55, cudaEglColorFormatBayer12GBRG = 56, cudaEglColorFormatBayer14RGGB = 57, cudaEglColorFormatBayer14BGGR = 58, cudaEglColorFormatBayer14GRBG = 59, cudaEglColorFormatBayer14GBRG = 60, cudaEglColorFormatBayer20RGGB = 61, cudaEglColorFormatBayer20BGGR = 62, cudaEglColorFormatBayer20GRBG = 63, cudaEglColorFormatBayer20GBRG = 64, cudaEglColorFormatYVU444Planar = 65, cudaEglColorFormatYVU422Planar = 66, cudaEglColorFormatYVU420Planar = 67, cudaEglColorFormatBayerIspRGGB = 68, cudaEglColorFormatBayerIspBGGR = 69, cudaEglColorFormatBayerIspGRBG = 70, cudaEglColorFormatBayerIspGBRG = 71 }
enum cudaEglFrameType { cudaEglFrameTypeArray = 0, cudaEglFrameTypePitch = 1 }
enum cudaEglResourceLocationFlags { cudaEglResourceLocationSysmem = 0x00, cudaEglResourceLocationVidmem = 0x01 }
enum cudaError { cudaSuccess = 0, cudaErrorInvalidValue = 1, cudaErrorMemoryAllocation = 2, cudaErrorInitializationError = 3, cudaErrorCudartUnloading = 4, cudaErrorProfilerDisabled = 5, cudaErrorProfilerNotInitialized = 6, cudaErrorProfilerAlreadyStarted = 7, cudaErrorProfilerAlreadyStopped = 8, cudaErrorInvalidConfiguration = 9, cudaErrorInvalidPitchValue = 12, cudaErrorInvalidSymbol = 13, cudaErrorInvalidHostPointer = 16, cudaErrorInvalidDevicePointer = 17, cudaErrorInvalidTexture = 18, cudaErrorInvalidTextureBinding = 19, cudaErrorInvalidChannelDescriptor = 20, cudaErrorInvalidMemcpyDirection = 21, cudaErrorAddressOfConstant = 22, cudaErrorTextureFetchFailed = 23, cudaErrorTextureNotBound = 24, cudaErrorSynchronizationError = 25, cudaErrorInvalidFilterSetting = 26, cudaErrorInvalidNormSetting = 27, cudaErrorMixedDeviceExecution = 28, cudaErrorNotYetImplemented = 31, cudaErrorMemoryValueTooLarge = 32, cudaErrorInsufficientDriver = 35, cudaErrorInvalidSurface = 37, cudaErrorDuplicateVariableName = 43, cudaErrorDuplicateTextureName = 44, cudaErrorDuplicateSurfaceName = 45, cudaErrorDevicesUnavailable = 46, cudaErrorIncompatibleDriverContext = 49, cudaErrorMissingConfiguration = 52, cudaErrorPriorLaunchFailure = 53, cudaErrorLaunchMaxDepthExceeded = 65, cudaErrorLaunchFileScopedTex = 66, cudaErrorLaunchFileScopedSurf = 67, cudaErrorSyncDepthExceeded = 68, cudaErrorLaunchPendingCountExceeded = 69, cudaErrorInvalidDeviceFunction = 98, cudaErrorNoDevice = 100, cudaErrorInvalidDevice = 101, cudaErrorStartupFailure = 127, cudaErrorInvalidKernelImage = 200, cudaErrorDeviceUninitilialized = 201, cudaErrorMapBufferObjectFailed = 205, cudaErrorUnmapBufferObjectFailed = 206, cudaErrorArrayIsMapped = 207, cudaErrorAlreadyMapped = 208, cudaErrorNoKernelImageForDevice = 209, cudaErrorAlreadyAcquired = 210, cudaErrorNotMapped = 211, cudaErrorNotMappedAsArray = 212, cudaErrorNotMappedAsPointer = 213, cudaErrorECCUncorrectable = 214, cudaErrorUnsupportedLimit = 215, cudaErrorDeviceAlreadyInUse = 216, cudaErrorPeerAccessUnsupported = 217, cudaErrorInvalidPtx = 218, cudaErrorInvalidGraphicsContext = 219, cudaErrorNvlinkUncorrectable = 220, cudaErrorJitCompilerNotFound = 221, cudaErrorInvalidSource = 300, cudaErrorFileNotFound = 301, cudaErrorSharedObjectSymbolNotFound = 302, cudaErrorSharedObjectInitFailed = 303, cudaErrorOperatingSystem = 304, cudaErrorInvalidResourceHandle = 400, cudaErrorIllegalState = 401, cudaErrorSymbolNotFound = 500, cudaErrorNotReady = 600, cudaErrorIllegalAddress = 700, cudaErrorLaunchOutOfResources = 701, cudaErrorLaunchTimeout = 702, cudaErrorLaunchIncompatibleTexturing = 703, cudaErrorPeerAccessAlreadyEnabled = 704, cudaErrorPeerAccessNotEnabled = 705, cudaErrorSetOnActiveProcess = 708, cudaErrorContextIsDestroyed = 709, cudaErrorAssert = 710, cudaErrorTooManyPeers = 711, cudaErrorHostMemoryAlreadyRegistered = 712, cudaErrorHostMemoryNotRegistered = 713, cudaErrorHardwareStackError = 714, cudaErrorIllegalInstruction = 715, cudaErrorMisalignedAddress = 716, cudaErrorInvalidAddressSpace = 717, cudaErrorInvalidPc = 718, cudaErrorLaunchFailure = 719, cudaErrorCooperativeLaunchTooLarge = 720, cudaErrorNotPermitted = 800, cudaErrorNotSupported = 801, cudaErrorSystemNotReady = 802, cudaErrorSystemDriverMismatch = 803, cudaErrorCompatNotSupportedOnDevice = 804, cudaErrorStreamCaptureUnsupported = 900, cudaErrorStreamCaptureInvalidated = 901, cudaErrorStreamCaptureMerge = 902, cudaErrorStreamCaptureUnmatched = 903, cudaErrorStreamCaptureUnjoined = 904, cudaErrorStreamCaptureIsolation = 905, cudaErrorStreamCaptureImplicit = 906, cudaErrorCapturedEvent = 907, cudaErrorStreamCaptureWrongThread = 908, cudaErrorUnknown = 999, cudaErrorApiFailureBase = 10000 }
enum cudaExternalMemoryHandleType { cudaExternalMemoryHandleTypeOpaqueFd = 1, cudaExternalMemoryHandleTypeOpaqueWin32 = 2, cudaExternalMemoryHandleTypeOpaqueWin32Kmt = 3, cudaExternalMemoryHandleTypeD3D12Heap = 4, cudaExternalMemoryHandleTypeD3D12Resource = 5 }
enum cudaExternalSemaphoreHandleType { cudaExternalSemaphoreHandleTypeOpaqueFd = 1, cudaExternalSemaphoreHandleTypeOpaqueWin32 = 2, cudaExternalSemaphoreHandleTypeOpaqueWin32Kmt = 3, cudaExternalSemaphoreHandleTypeD3D12Fence = 4 }
enum cudaFuncAttribute { cudaFuncAttributeMaxDynamicSharedMemorySize = 8, cudaFuncAttributePreferredSharedMemoryCarveout = 9 }
enum cudaFuncCache { cudaFuncCachePreferNone = 0, cudaFuncCachePreferShared = 1, cudaFuncCachePreferL1 = 2, cudaFuncCachePreferEqual = 3 }
enum cudaGraphicsCubeFace { cudaGraphicsCubeFacePositiveX = 0x00, cudaGraphicsCubeFaceNegativeX = 0x01, cudaGraphicsCubeFacePositiveY = 0x02, cudaGraphicsCubeFaceNegativeY = 0x03, cudaGraphicsCubeFacePositiveZ = 0x04, cudaGraphicsCubeFaceNegativeZ = 0x05 }
enum cudaGraphicsMapFlags { cudaGraphicsMapFlagsNone = 0, cudaGraphicsMapFlagsReadOnly = 1, cudaGraphicsMapFlagsWriteDiscard = 2 }
enum cudaGraphicsRegisterFlags { cudaGraphicsRegisterFlagsNone = 0, cudaGraphicsRegisterFlagsReadOnly = 1, cudaGraphicsRegisterFlagsWriteDiscard = 2, cudaGraphicsRegisterFlagsSurfaceLoadStore = 4, cudaGraphicsRegisterFlagsTextureGather = 8 }
enum cudaGraphNodeType { cudaGraphNodeTypeKernel = 0x00, cudaGraphNodeTypeMemcpy = 0x01, cudaGraphNodeTypeMemset = 0x02, cudaGraphNodeTypeHost = 0x03, cudaGraphNodeTypeGraph = 0x04, cudaGraphNodeTypeEmpty = 0x05 }
enum cudaLimit { cudaLimitStackSize = 0x00, cudaLimitPrintfFifoSize = 0x01, cudaLimitMallocHeapSize = 0x02, cudaLimitDevRuntimeSyncDepth = 0x03, cudaLimitDevRuntimePendingLaunchCount = 0x04, cudaLimitMaxL2FetchGranularity = 0x05 }
enum cudaMemcpyKind { cudaMemcpyHostToHost = 0, cudaMemcpyHostToDevice = 1, cudaMemcpyDeviceToHost = 2, cudaMemcpyDeviceToDevice = 3, cudaMemcpyDefault = 4 }
enum cudaMemoryAdvise { cudaMemAdviseSetReadMostly = 1, cudaMemAdviseUnsetReadMostly = 2, cudaMemAdviseSetPreferredLocation = 3, cudaMemAdviseUnsetPreferredLocation = 4, cudaMemAdviseSetAccessedBy = 5, cudaMemAdviseUnsetAccessedBy = 6 }
enum cudaMemoryType { cudaMemoryTypeUnregistered = 0, cudaMemoryTypeHost = 1, cudaMemoryTypeDevice = 2, cudaMemoryTypeManaged = 3 }
enum cudaMemRangeAttribute { cudaMemRangeAttributeReadMostly = 1, cudaMemRangeAttributePreferredLocation = 2, cudaMemRangeAttributeAccessedBy = 3, cudaMemRangeAttributeLastPrefetchLocation = 4 }
enum cudaOutputMode { cudaKeyValuePair = 0x00, cudaCSV = 0x01 }
enum cudaResourceType { cudaResourceTypeArray = 0x00, cudaResourceTypeMipmappedArray = 0x01, cudaResourceTypeLinear = 0x02, cudaResourceTypePitch2D = 0x03 }
enum cudaResourceViewFormat { cudaResViewFormatNone = 0x00, cudaResViewFormatUnsignedChar1 = 0x01, cudaResViewFormatUnsignedChar2 = 0x02, cudaResViewFormatUnsignedChar4 = 0x03, cudaResViewFormatSignedChar1 = 0x04, cudaResViewFormatSignedChar2 = 0x05, cudaResViewFormatSignedChar4 = 0x06, cudaResViewFormatUnsignedShort1 = 0x07, cudaResViewFormatUnsignedShort2 = 0x08, cudaResViewFormatUnsignedShort4 = 0x09, cudaResViewFormatSignedShort1 = 0x0a, cudaResViewFormatSignedShort2 = 0x0b, cudaResViewFormatSignedShort4 = 0x0c, cudaResViewFormatUnsignedInt1 = 0x0d, cudaResViewFormatUnsignedInt2 = 0x0e, cudaResViewFormatUnsignedInt4 = 0x0f, cudaResViewFormatSignedInt1 = 0x10, cudaResViewFormatSignedInt2 = 0x11, cudaResViewFormatSignedInt4 = 0x12, cudaResViewFormatHalf1 = 0x13, cudaResViewFormatHalf2 = 0x14, cudaResViewFormatHalf4 = 0x15, cudaResViewFormatFloat1 = 0x16, cudaResViewFormatFloat2 = 0x17, cudaResViewFormatFloat4 = 0x18, cudaResViewFormatUnsignedBlockCompressed1 = 0x19, cudaResViewFormatUnsignedBlockCompressed2 = 0x1a, cudaResViewFormatUnsignedBlockCompressed3 = 0x1b, cudaResViewFormatUnsignedBlockCompressed4 = 0x1c, cudaResViewFormatSignedBlockCompressed4 = 0x1d, cudaResViewFormatUnsignedBlockCompressed5 = 0x1e, cudaResViewFormatSignedBlockCompressed5 = 0x1f, cudaResViewFormatUnsignedBlockCompressed6H = 0x20, cudaResViewFormatSignedBlockCompressed6H = 0x21, cudaResViewFormatUnsignedBlockCompressed7 = 0x22 }
enum cudaSharedCarveout { cudaSharedmemCarveoutDefault = -1, cudaSharedmemCarveoutMaxShared = 100, cudaSharedmemCarveoutMaxL1 = 0 }
enum cudaSharedMemConfig
enum cudaStreamCaptureMode
enum cudaStreamCaptureStatus { cudaStreamCaptureStatusNone = 0, cudaStreamCaptureStatusActive = 1, cudaStreamCaptureStatusInvalidated = 2 }
enum cudaSurfaceBoundaryMode { cudaBoundaryModeZero = 0, cudaBoundaryModeClamp = 1, cudaBoundaryModeTrap = 2 }
enum cudaSurfaceFormatMode { cudaFormatModeForced = 0, cudaFormatModeAuto = 1 }
enum cudaTextureAddressMode { cudaAddressModeWrap = 0, cudaAddressModeClamp = 1, cudaAddressModeMirror = 2, cudaAddressModeBorder = 3 }
enum cudaTextureFilterMode { cudaFilterModePoint = 0, cudaFilterModeLinear = 1 }
enum cudaTextureReadMode { cudaReadModeElementType = 0, cudaReadModeNormalizedFloat = 1 }

Maximum number of planes per frame

CUDA IPC Handle Size

Must be set in cudaExternalMemoryGetMappedMipmappedArray if the mipmapped array is used as a color target in a graphics API

Must be set in cudaMalloc3DArray to create a cubemap CUDA array

Default CUDA array allocation flag

Must be set in cudaMalloc3DArray to create a layered CUDA array

Must be set in cudaMallocArray or cudaMalloc3DArray in order to bind surfaces to the CUDA array

Must be set in cudaMallocArray or cudaMalloc3DArray in order to perform texture gather operations on the CUDA array

If set, any subsequent work pushed in a stream that participated in a call to cudaLaunchCooperativeKernelMultiDevice will only wait for the kernel launched on the GPU corresponding to that stream to complete before it begins execution.

If set, each kernel launched as part of cudaLaunchCooperativeKernelMultiDevice only waits for prior work in the stream corresponding to that GPU to complete before the kernel begins execution.

Device id that represents the CPU

Device flag - Use blocking synchronization

Deprecated

This flag was deprecated as of CUDA 4.0 and replaced with cudaDeviceScheduleBlockingSync.

Device flag - Keep local memory allocation after launch

Device flag - Support mapped pinned allocations

Device flags mask

Empty device properties

Device flag - Automatic scheduling

Device flag - Use blocking synchronization

Device schedule flags mask

Device flag - Spin default scheduling

Device flag - Yield default scheduling

Event uses blocking synchronization

Default event flag

Event will not record timing data

Event is suitable for interprocess use. cudaEventDisableTiming must be set

Indicates that the external memory object is a dedicated resource

Default page-locked allocation flag

Map allocation into device space

Pinned memory accessible by all CUDA contexts

Write-combined memory

Default host memory registration flag

Memory-mapped I/O space

Map registered memory into device space

Pinned memory accessible by all CUDA contexts

Device id that represents an invalid device

Automatically enable peer access between remote devices as needed

Memory can be accessed by any stream on any device

Memory cannot be accessed by any stream on any device

Memory can only be accessed by a single stream on the associated device

Default behavior

Assume global caching is enabled and cannot be automatically turned off

Default peer addressing enable flag

Default stream flag

Legacy stream handle

Stream handle that can be passed as a cudaStream_t to use an implicit stream with legacy synchronization behavior.

See details of the .

Stream does not synchronize with stream 0 (the NULL stream)

Per-thread stream handle

Stream handle that can be passed as a cudaStream_t to use an implicit stream with per-thread synchronization behavior.

See details of the .

typedef struct cudaArray* cudaArray_const_t

CUDA array (as source copy argument)

typedef struct cudaArray* cudaArray_t

CUDA array

CUDA EGLSream Connection

typedef enum cudaError cudaError_t

CUDA Error types

CUDA event types

CUDA external memory

CUDA external semaphore

CUDA graph

CUDA executable (launchable) graph

CUDA graphics resource types

CUDA graph node.

CUDA host function

Parameters:

userData Argument value passed to the function

typedef struct cudaMipmappedArray* cudaMipmappedArray_const_t

CUDA mipmapped array (as source argument)

typedef struct cudaMipmappedArray* cudaMipmappedArray_t

CUDA mipmapped array

typedef enum cudaOutputMode cudaOutputMode_t

CUDA output file modes

CUDA stream

typedef unsigned long long cudaSurfaceObject_t

An opaque value that represents a CUDA Surface object

typedef unsigned long long cudaTextureObject_t

An opaque value that represents a CUDA texture object

enum cudaCGScope

CUDA cooperative group scope

Enumerator:

Invalid cooperative group scope
Scope represented by a grid_group
Scope represented by a multi_grid_group

enum cudaChannelFormatKind

Channel format kind

Enumerator:

Signed channel format
Unsigned channel format
Float channel format
No channel format

enum cudaComputeMode

CUDA device compute modes

Enumerator:

Default compute mode (Multiple threads can use cudaSetDevice() with this device)
Compute-exclusive-thread mode (Only one thread in one process will be able to use cudaSetDevice() with this device)
Compute-prohibited mode (No threads can use cudaSetDevice() with this device)
Compute-exclusive-process mode (Many threads in one process will be able to use cudaSetDevice() with this device)

enum cudaDeviceAttr

CUDA device attributes

Enumerator:

Maximum number of threads per block
Maximum block dimension X
Maximum block dimension Y
Maximum block dimension Z
Maximum grid dimension X
Maximum grid dimension Y
Maximum grid dimension Z
Maximum shared memory available per block in bytes
Memory available on device for __constant__ variables in a CUDA C kernel in bytes
Warp size in threads
Maximum pitch in bytes allowed by memory copies
Maximum number of 32-bit registers available per block
Peak clock frequency in kilohertz
Alignment requirement for textures
Device can possibly copy memory and execute a kernel concurrently
Number of multiprocessors on device
Specifies whether there is a run time limit on kernels
Device is integrated with host memory
Device can map host memory into CUDA address space
Compute mode (See cudaComputeMode for details)
Maximum 1D texture width
Maximum 2D texture width
Maximum 2D texture height
Maximum 3D texture width
Maximum 3D texture height
Maximum 3D texture depth
Maximum 2D layered texture width
Maximum 2D layered texture height
Maximum layers in a 2D layered texture
Alignment requirement for surfaces
Device can possibly execute multiple kernels concurrently
Device has ECC support enabled
PCI bus ID of the device
PCI device ID of the device
Device is using TCC driver model
Peak memory clock frequency in kilohertz
Global memory bus width in bits
Size of L2 cache in bytes
Maximum resident threads per multiprocessor
Number of asynchronous engines
Device shares a unified address space with the host
Maximum 1D layered texture width
Maximum layers in a 1D layered texture
Maximum 2D texture width if cudaArrayTextureGather is set
Maximum 2D texture height if cudaArrayTextureGather is set
Alternate maximum 3D texture width
Alternate maximum 3D texture height
Alternate maximum 3D texture depth
PCI domain ID of the device
Pitch alignment requirement for textures
Maximum cubemap texture width/height
Maximum cubemap layered texture width/height
Maximum layers in a cubemap layered texture
Maximum 1D surface width
Maximum 2D surface width
Maximum 2D surface height
Maximum 3D surface width
Maximum 3D surface height
Maximum 3D surface depth
Maximum 1D layered surface width
Maximum layers in a 1D layered surface
Maximum 2D layered surface width
Maximum 2D layered surface height
Maximum layers in a 2D layered surface
Maximum cubemap surface width
Maximum cubemap layered surface width
Maximum layers in a cubemap layered surface
Maximum 1D linear texture width
Maximum 2D linear texture width
Maximum 2D linear texture height
Maximum 2D linear texture pitch in bytes
Maximum mipmapped 2D texture width
Maximum mipmapped 2D texture height
Major compute capability version number
Minor compute capability version number
Maximum mipmapped 1D texture width
Device supports stream priorities
Device supports caching globals in L1
Device supports caching locals in L1
Maximum shared memory available per multiprocessor in bytes
Maximum number of 32-bit registers available per multiprocessor
Device can allocate managed memory on this system
Device is on a multi-GPU board
Unique identifier for a group of devices on the same multi-GPU board
Link between the device and the host supports native atomic operations
Ratio of single precision performance (in floating-point operations per second) to double precision performance
Device supports coherently accessing pageable memory without calling cudaHostRegister on it
Device can coherently access managed memory concurrently with the CPU
Device supports Compute Preemption
Device can access host registered memory at the same virtual address as the CPU
Device supports launching cooperative kernels via cudaLaunchCooperativeKernel
Device can participate in cooperative kernels launched via cudaLaunchCooperativeKernelMultiDevice
The maximum optin shared memory per block. This value may vary by chip. See cudaFuncSetAttribute
Device supports flushing of outstanding remote writes.
Device supports host memory registration via cudaHostRegister.
Device accesses pageable memory via the host's page tables.
Host can directly access managed memory on the device without migration.

enum cudaDeviceP2PAttr

CUDA device P2P attributes

Enumerator:

A relative value indicating the performance of the link between two devices
Peer access is enabled
Native atomic operation over the link supported
Accessing CUDA arrays over the link supported

enum cudaEglColorFormat

CUDA EGL Color Format - The different planar and multiplanar formats currently supported for CUDA_EGL interops.

Enumerator:

Y, U, V in three surfaces, each in a separate surface, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Y, UV in two surfaces (UV as one surface) with VU byte ordering, width, height ratio same as YUV420Planar.
Y, U, V each in a separate surface, U/V width = 1/2 Y width, U/V height = Y height.
Y, UV in two surfaces with VU byte ordering, width, height ratio same as YUV422Planar.
R/G/B three channels in one surface with BGR byte ordering. Only pitch linear format supported.
R/G/B three channels in one surface with RGB byte ordering. Only pitch linear format supported.
R/G/B/A four channels in one surface with BGRA byte ordering.
R/G/B/A four channels in one surface with ABGR byte ordering.
single luminance channel in one surface.
single color channel in one surface.
Y, U, V in three surfaces, each in a separate surface, U/V width = Y width, U/V height = Y height.
Y, UV in two surfaces (UV as one surface) with VU byte ordering, width, height ratio same as YUV444Planar.
Y, U, V in one surface, interleaved as UYVY.
Y, U, V in one surface, interleaved as YUYV.
R/G/B/A four channels in one surface with RGBA byte ordering.
R/G/B/A four channels in one surface with ARGB byte ordering.
Alpha color format - one channel in one surface.
R/G color format - two channels in one surface with GR byte ordering
Y, U, V, A four channels in one surface, interleaved as VUYA.
Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = Y width, U/V height = Y height.
Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = Y height.
Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Y10, V10U10 in two surfaces (VU as one surface) with UV byte ordering, U/V width = Y width, U/V height = Y height.
Y10, V10U10 in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Y12, V12U12 in two surfaces (VU as one surface) with UV byte ordering, U/V width = Y width, U/V height = Y height.
Y12, V12U12 in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Extended Range Y, U, V in one surface, interleaved as YVYU.
Extended Range Y, U, V in one surface, interleaved as YUYV.
Extended Range Y, U, V in one surface, interleaved as UYVY.
Extended Range Y, U, V in one surface, interleaved as VYUY.
Extended Range Y, U, V three channels in one surface, interleaved as VUY. Only pitch linear format supported.
Extended Range Y, U, V, A four channels in one surface, interleaved as AVUY.
Extended Range Y, U, V, A four channels in one surface, interleaved as VUYA.
Extended Range Y, U, V in three surfaces, U/V width = Y width, U/V height = Y height.
Extended Range Y, U, V in three surfaces, U/V width = 1/2 Y width, U/V height = Y height.
Extended Range Y, U, V in three surfaces, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Extended Range Y, UV in two surfaces (UV as one surface) with VU byte ordering, U/V width = Y width, U/V height = Y height.
Extended Range Y, UV in two surfaces (UV as one surface) with VU byte ordering, U/V width = 1/2 Y width, U/V height = Y height.
Extended Range Y, UV in two surfaces (UV as one surface) with VU byte ordering, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Extended Range Y, V, U in three surfaces, U/V width = Y width, U/V height = Y height.
Extended Range Y, V, U in three surfaces, U/V width = 1/2 Y width, U/V height = Y height.
Extended Range Y, V, U in three surfaces, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Extended Range Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = Y width, U/V height = Y height.
Extended Range Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = Y height.
Extended Range Y, VU in two surfaces (VU as one surface) with UV byte ordering, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Bayer format - one channel in one surface with interleaved RGGB ordering.
Bayer format - one channel in one surface with interleaved BGGR ordering.
Bayer format - one channel in one surface with interleaved GRBG ordering.
Bayer format - one channel in one surface with interleaved GBRG ordering.
Bayer10 format - one channel in one surface with interleaved RGGB ordering. Out of 16 bits, 10 bits used 6 bits No-op.
Bayer10 format - one channel in one surface with interleaved BGGR ordering. Out of 16 bits, 10 bits used 6 bits No-op.
Bayer10 format - one channel in one surface with interleaved GRBG ordering. Out of 16 bits, 10 bits used 6 bits No-op.
Bayer10 format - one channel in one surface with interleaved GBRG ordering. Out of 16 bits, 10 bits used 6 bits No-op.
Bayer12 format - one channel in one surface with interleaved RGGB ordering. Out of 16 bits, 12 bits used 4 bits No-op.
Bayer12 format - one channel in one surface with interleaved BGGR ordering. Out of 16 bits, 12 bits used 4 bits No-op.
Bayer12 format - one channel in one surface with interleaved GRBG ordering. Out of 16 bits, 12 bits used 4 bits No-op.
Bayer12 format - one channel in one surface with interleaved GBRG ordering. Out of 16 bits, 12 bits used 4 bits No-op.
Bayer14 format - one channel in one surface with interleaved RGGB ordering. Out of 16 bits, 14 bits used 2 bits No-op.
Bayer14 format - one channel in one surface with interleaved BGGR ordering. Out of 16 bits, 14 bits used 2 bits No-op.
Bayer14 format - one channel in one surface with interleaved GRBG ordering. Out of 16 bits, 14 bits used 2 bits No-op.
Bayer14 format - one channel in one surface with interleaved GBRG ordering. Out of 16 bits, 14 bits used 2 bits No-op.
Bayer20 format - one channel in one surface with interleaved RGGB ordering. Out of 32 bits, 20 bits used 12 bits No-op.
Bayer20 format - one channel in one surface with interleaved BGGR ordering. Out of 32 bits, 20 bits used 12 bits No-op.
Bayer20 format - one channel in one surface with interleaved GRBG ordering. Out of 32 bits, 20 bits used 12 bits No-op.
Bayer20 format - one channel in one surface with interleaved GBRG ordering. Out of 32 bits, 20 bits used 12 bits No-op.
Y, V, U in three surfaces, each in a separate surface, U/V width = Y width, U/V height = Y height.
Y, V, U in three surfaces, each in a separate surface, U/V width = 1/2 Y width, U/V height = Y height.
Y, V, U in three surfaces, each in a separate surface, U/V width = 1/2 Y width, U/V height = 1/2 Y height.
Nvidia proprietary Bayer ISP format - one channel in one surface with interleaved RGGB ordering and mapped to opaque integer datatype.
Nvidia proprietary Bayer ISP format - one channel in one surface with interleaved BGGR ordering and mapped to opaque integer datatype.
Nvidia proprietary Bayer ISP format - one channel in one surface with interleaved GRBG ordering and mapped to opaque integer datatype.
Nvidia proprietary Bayer ISP format - one channel in one surface with interleaved GBRG ordering and mapped to opaque integer datatype.

enum cudaEglFrameType

CUDA EglFrame type - array or pointer

Enumerator:

Frame type CUDA array
Frame type CUDA pointer

enum cudaEglResourceLocationFlags

Resource location flags- sysmem or vidmem

For CUDA context on iGPU, since video and system memory are equivalent - these flags will not have an effect on the execution.

For CUDA context on dGPU, applications can use the flag cudaEglResourceLocationFlags to give a hint about the desired location.

cudaEglResourceLocationSysmem - the frame data is made resident on the system memory to be accessed by CUDA.

cudaEglResourceLocationVidmem - the frame data is made resident on the dedicated video memory to be accessed by CUDA.

There may be an additional latency due to new allocation and data migration, if the frame is produced on a different memory.

Enumerator:

Resource location sysmem
Resource location vidmem

enum cudaError

CUDA error types

Enumerator:

The API call returned with no errors. In the case of query calls, this also means that the operation being queried is complete (see cudaEventQuery() and cudaStreamQuery()).
This indicates that one or more of the parameters passed to the API call is not within an acceptable range of values.
The API call failed because it was unable to allocate enough memory to perform the requested operation.
The API call failed because the CUDA driver and runtime could not be initialized.
This indicates that a CUDA Runtime API call cannot be executed because it is being called during process shut down, at a point in time after CUDA driver has been unloaded.
This indicates profiler is not initialized for this run. This can happen when the application is running with external profiling tools like visual profiler.
Deprecated
This error return is deprecated as of CUDA 5.0. It is no longer an error to attempt to enable/disable the profiling via cudaProfilerStart or cudaProfilerStop without initialization.
Deprecated
This error return is deprecated as of CUDA 5.0. It is no longer an error to call cudaProfilerStart() when profiling is already enabled.
Deprecated
This error return is deprecated as of CUDA 5.0. It is no longer an error to call cudaProfilerStop() when profiling is already disabled.
This indicates that a kernel launch is requesting resources that can never be satisfied by the current device. Requesting more shared memory per block than the device supports will trigger this error, as will requesting too many threads or blocks. See cudaDeviceProp for more device limitations.
This indicates that one or more of the pitch-related parameters passed to the API call is not within the acceptable range for pitch.
This indicates that the symbol name/identifier passed to the API call is not a valid name or identifier.
This indicates that at least one host pointer passed to the API call is not a valid host pointer.

Deprecated

This error return is deprecated as of CUDA 10.1.
This indicates that at least one device pointer passed to the API call is not a valid device pointer.

Deprecated

This error return is deprecated as of CUDA 10.1.
This indicates that the texture passed to the API call is not a valid texture.
This indicates that the texture binding is not valid. This occurs if you call cudaGetTextureAlignmentOffset() with an unbound texture.
This indicates that the channel descriptor passed to the API call is not valid. This occurs if the format is not one of the formats specified by cudaChannelFormatKind, or if one of the dimensions is invalid.
This indicates that the direction of the memcpy passed to the API call is not one of the types specified by cudaMemcpyKind.
This indicated that the user has taken the address of a constant variable, which was forbidden up until the CUDA 3.1 release.

Deprecated

This error return is deprecated as of CUDA 3.1. Variables in constant memory may now have their address taken by the runtime via cudaGetSymbolAddress().
This indicated that a texture fetch was not able to be performed. This was previously used for device emulation of texture operations.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This indicated that a texture was not bound for access. This was previously used for device emulation of texture operations.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This indicated that a synchronization operation had failed. This was previously used for some device emulation functions.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This indicates that a non-float texture was being accessed with linear filtering. This is not supported by CUDA.
This indicates that an attempt was made to read a non-float texture as a normalized float. This is not supported by CUDA.
Mixing of device and device emulation code was not allowed.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This indicates that the API call is not yet implemented. Production releases of CUDA will never return this error.

Deprecated

This error return is deprecated as of CUDA 4.1.
This indicated that an emulated device pointer exceeded the 32-bit address range.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This indicates that the installed NVIDIA CUDA driver is older than the CUDA runtime library. This is not a supported configuration. Users should install an updated NVIDIA display driver to allow the application to run.
This indicates that the surface passed to the API call is not a valid surface.
This indicates that multiple global or constant variables (across separate CUDA source files in the application) share the same string name.
This indicates that multiple textures (across separate CUDA source files in the application) share the same string name.
This indicates that multiple surfaces (across separate CUDA source files in the application) share the same string name.
This indicates that all CUDA devices are busy or unavailable at the current time. Devices are often busy/unavailable due to use of cudaComputeModeExclusive, cudaComputeModeProhibited or when long running CUDA kernels have filled up the GPU and are blocking new work from starting. They can also be unavailable due to memory constraints on a device that already has active CUDA work being performed.
This indicates that the current context is not compatible with this the CUDA Runtime. This can only occur if you are using CUDA Runtime/Driver interoperability and have created an existing Driver context using the driver API. The Driver context may be incompatible either because the Driver context was created using an older version of the API, because the Runtime API call expects a primary driver context and the Driver context is not primary, or because the Driver context has been destroyed. Please see Interactions with the CUDA Driver API' for more information.
The device function being invoked (usually via cudaLaunchKernel()) was not previously configured via the cudaConfigureCall() function.
This indicated that a previous kernel launch failed. This was previously used for device emulation of kernel launches.

Deprecated

This error return is deprecated as of CUDA 3.1. Device emulation mode was removed with the CUDA 3.1 release.
This error indicates that a device runtime grid launch did not occur because the depth of the child grid would exceed the maximum supported number of nested grid launches.
This error indicates that a grid launch did not occur because the kernel uses file-scoped textures which are unsupported by the device runtime. Kernels launched via the device runtime only support textures created with the Texture Object API's.
This error indicates that a grid launch did not occur because the kernel uses file-scoped surfaces which are unsupported by the device runtime. Kernels launched via the device runtime only support surfaces created with the Surface Object API's.
This error indicates that a call to cudaDeviceSynchronize made from the device runtime failed because the call was made at grid depth greater than than either the default (2 levels of grids) or user specified device limit cudaLimitDevRuntimeSyncDepth. To be able to synchronize on launched grids at a greater depth successfully, the maximum nested depth at which cudaDeviceSynchronize will be called must be specified with the cudaLimitDevRuntimeSyncDepth limit to the cudaDeviceSetLimit api before the host-side launch of a kernel using the device runtime. Keep in mind that additional levels of sync depth require the runtime to reserve large amounts of device memory that cannot be used for user allocations.
This error indicates that a device runtime grid launch failed because the launch would exceed the limit cudaLimitDevRuntimePendingLaunchCount. For this launch to proceed successfully, cudaDeviceSetLimit must be called to set the cudaLimitDevRuntimePendingLaunchCount to be higher than the upper bound of outstanding launches that can be issued to the device runtime. Keep in mind that raising the limit of pending device runtime launches will require the runtime to reserve device memory that cannot be used for user allocations.
The requested device function does not exist or is not compiled for the proper device architecture.
This indicates that no CUDA-capable devices were detected by the installed CUDA driver.
This indicates that the device ordinal supplied by the user does not correspond to a valid CUDA device.
This indicates an internal startup failure in the CUDA runtime.
This indicates that the device kernel image is invalid.
This most frequently indicates that there is no context bound to the current thread. This can also be returned if the context passed to an API call is not a valid handle (such as a context that has had cuCtxDestroy() invoked on it). This can also be returned if a user mixes different API versions (i.e. 3010 context with 3020 API calls). See cuCtxGetApiVersion() for more details.
This indicates that the buffer object could not be mapped.
This indicates that the buffer object could not be unmapped.
This indicates that the specified array is currently mapped and thus cannot be destroyed.
This indicates that the resource is already mapped.
This indicates that there is no kernel image available that is suitable for the device. This can occur when a user specifies code generation options for a particular CUDA source file that do not include the corresponding device configuration.
This indicates that a resource has already been acquired.
This indicates that a resource is not mapped.
This indicates that a mapped resource is not available for access as an array.
This indicates that a mapped resource is not available for access as a pointer.
This indicates that an uncorrectable ECC error was detected during execution.
This indicates that the cudaLimit passed to the API call is not supported by the active device.
This indicates that a call tried to access an exclusive-thread device that is already in use by a different thread.
This error indicates that P2P access is not supported across the given devices.
A PTX compilation failed. The runtime may fall back to compiling PTX if an application does not contain a suitable binary for the current device.
This indicates an error with the OpenGL or DirectX context.
This indicates that an uncorrectable NVLink error was detected during the execution.
This indicates that the PTX JIT compiler library was not found. The JIT Compiler library is used for PTX compilation. The runtime may fall back to compiling PTX if an application does not contain a suitable binary for the current device.
This indicates that the device kernel source is invalid.
This indicates that the file specified was not found.
This indicates that a link to a shared object failed to resolve.
This indicates that initialization of a shared object failed.
This error indicates that an OS call failed.
This indicates that a resource handle passed to the API call was not valid. Resource handles are opaque types like cudaStream_t and cudaEvent_t.
This indicates that a resource required by the API call is not in a valid state to perform the requested operation.
This indicates that a named symbol was not found. Examples of symbols are global/constant variable names, texture names, and surface names.
This indicates that asynchronous operations issued previously have not completed yet. This result is not actually an error, but must be indicated differently than cudaSuccess (which indicates completion). Calls that may return this value include cudaEventQuery() and cudaStreamQuery().
The device encountered a load or store instruction on an invalid memory address. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
This indicates that a launch did not occur because it did not have appropriate resources. Although this error is similar to cudaErrorInvalidConfiguration, this error usually indicates that the user has attempted to pass too many arguments to the device kernel, or the kernel launch specifies too many threads for the kernel's register count.
This indicates that the device kernel took too long to execute. This can only occur if timeouts are enabled - see the device property kernelExecTimeoutEnabled for more information. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
This error indicates a kernel launch that uses an incompatible texturing mode.
This error indicates that a call to cudaDeviceEnablePeerAccess() is trying to re-enable peer addressing on from a context which has already had peer addressing enabled.
This error indicates that cudaDeviceDisablePeerAccess() is trying to disable peer addressing which has not been enabled yet via cudaDeviceEnablePeerAccess().
This indicates that the user has called cudaSetValidDevices(), cudaSetDeviceFlags(), cudaD3D9SetDirect3DDevice(), cudaD3D10SetDirect3DDevice, cudaD3D11SetDirect3DDevice(), or cudaVDPAUSetVDPAUDevice() after initializing the CUDA runtime by calling non-device management operations (allocating memory and launching kernels are examples of non-device management operations). This error can also be returned if using runtime/driver interoperability and there is an existing CUcontext active on the host thread.
This error indicates that the context current to the calling thread has been destroyed using cuCtxDestroy, or is a primary context which has not yet been initialized.
An assert triggered in device code during kernel execution. The device cannot be used again. All existing allocations are invalid. To continue using CUDA, the process must be terminated and relaunched.
This error indicates that the hardware resources required to enable peer access have been exhausted for one or more of the devices passed to cudaEnablePeerAccess().
This error indicates that the memory range passed to cudaHostRegister() has already been registered.
This error indicates that the pointer passed to cudaHostUnregister() does not correspond to any currently registered memory region.
Device encountered an error in the call stack during kernel execution, possibly due to stack corruption or exceeding the stack size limit. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
The device encountered an illegal instruction during kernel execution This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
The device encountered a load or store instruction on a memory address which is not aligned. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
While executing a kernel, the device encountered an instruction which can only operate on memory locations in certain address spaces (global, shared, or local), but was supplied a memory address not belonging to an allowed address space. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
The device encountered an invalid program counter. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
An exception occurred on the device while executing a kernel. Common causes include dereferencing an invalid device pointer and accessing out of bounds shared memory. Less common cases can be system specific - more information about these cases can be found in the system specific user guide. This leaves the process in an inconsistent state and any further CUDA work will return the same error. To continue using CUDA, the process must be terminated and relaunched.
This error indicates that the number of blocks launched per grid for a kernel that was launched via either cudaLaunchCooperativeKernel or cudaLaunchCooperativeKernelMultiDevice exceeds the maximum number of blocks as allowed by cudaOccupancyMaxActiveBlocksPerMultiprocessor or cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags times the number of multiprocessors as specified by the device attribute cudaDevAttrMultiProcessorCount.
This error indicates the attempted operation is not permitted.
This error indicates the attempted operation is not supported on the current system or device.
This error indicates that the system is not yet ready to start any CUDA work. To continue using CUDA, verify the system configuration is in a valid state and all required driver daemons are actively running. More information about this error can be found in the system specific user guide.
This error indicates that there is a mismatch between the versions of the display driver and the CUDA driver. Refer to the compatibility documentation for supported versions.
This error indicates that the system was upgraded to run with forward compatibility but the visible hardware detected by CUDA does not support this configuration. Refer to the compatibility documentation for the supported hardware matrix or ensure that only supported hardware is visible during initialization via the CUDA_VISIBLE_DEVICES environment variable.
The operation is not permitted when the stream is capturing.
The current capture sequence on the stream has been invalidated due to a previous error.
The operation would have resulted in a merge of two independent capture sequences.
The capture was not initiated in this stream.
The capture sequence contains a fork that was not joined to the primary stream.
A dependency would have been created which crosses the capture sequence boundary. Only implicit in-stream ordering dependencies are allowed to cross the boundary.
The operation would have resulted in a disallowed implicit dependency on a current capture sequence from cudaStreamLegacy.
The operation is not permitted on an event which was last recorded in a capturing stream.
A stream capture sequence not initiated with the cudaStreamCaptureModeRelaxed argument to cudaStreamBeginCapture was passed to cudaStreamEndCapture in a different thread.
This indicates that an unknown internal error has occurred.
Any unhandled CUDA driver error is added to this value and returned via the runtime. Production releases of CUDA should not return such errors.

Deprecated

This error return is deprecated as of CUDA 4.1.

enum cudaExternalMemoryHandleType

External memory handle types

Enumerator:

Handle is an opaque file descriptor
Handle is an opaque shared NT handle
Handle is an opaque, globally shared handle
Handle is a D3D12 heap object
Handle is a D3D12 committed resource

enum cudaExternalSemaphoreHandleType

External semaphore handle types

Enumerator:

Handle is an opaque file descriptor
Handle is an opaque shared NT handle
Handle is an opaque, globally shared handle
Handle is a shared NT handle referencing a D3D12 fence object

enum cudaFuncAttribute

CUDA function attributes that can be set using cudaFuncSetAttribute

Enumerator:

Maximum dynamic shared memory size
Preferred shared memory-L1 cache split

enum cudaFuncCache

CUDA function cache configurations

Enumerator:

Default function cache configuration, no preference
Prefer larger shared memory and smaller L1 cache
Prefer larger L1 cache and smaller shared memory
Prefer equal size L1 cache and shared memory

enum cudaGraphicsCubeFace

CUDA graphics interop array indices for cube maps

Enumerator:

Positive X face of cubemap
Negative X face of cubemap
Positive Y face of cubemap
Negative Y face of cubemap
Positive Z face of cubemap
Negative Z face of cubemap

enum cudaGraphicsMapFlags

CUDA graphics interop map flags

Enumerator:

Default; Assume resource can be read/written
CUDA will not write to this resource
CUDA will only write to and will not read from this resource

enum cudaGraphicsRegisterFlags

CUDA graphics interop register flags

Enumerator:

Default
CUDA will not write to this resource
CUDA will only write to and will not read from this resource
CUDA will bind this resource to a surface reference
CUDA will perform texture gather operations on this resource

enum cudaGraphNodeType

CUDA Graph node types

Enumerator:

GPU kernel node
Memcpy node
Memset node
Host (executable) node
Node which executes an embedded graph
Empty (no-op) node

enum cudaLimit

CUDA Limits

Enumerator:

GPU thread stack size
GPU printf FIFO size
GPU malloc heap size
GPU device runtime synchronize depth
GPU device runtime pending launch count
A value between 0 and 128 that indicates the maximum fetch granularity of L2 (in Bytes). This is a hint

enum cudaMemcpyKind

CUDA memory copy types

Enumerator:

Host -> Host
Host -> Device
Device -> Host
Device -> Device
Direction of the transfer is inferred from the pointer values. Requires unified virtual addressing

enum cudaMemoryAdvise

CUDA Memory Advise values

Enumerator:

Data will mostly be read and only occasionally be written to
Undo the effect of cudaMemAdviseSetReadMostly
Set the preferred location for the data as the specified device
Clear the preferred location for the data
Data will be accessed by the specified device, so prevent page faults as much as possible
Let the Unified Memory subsystem decide on the page faulting policy for the specified device

enum cudaMemoryType

CUDA memory types

Enumerator:

Unregistered memory
Host memory
Device memory
Managed memory

enum cudaMemRangeAttribute

CUDA range attributes

Enumerator:

Whether the range will mostly be read and only occasionally be written to
The preferred location of the range
Memory range has cudaMemAdviseSetAccessedBy set for specified device
The last location to which the range was prefetched

enum cudaOutputMode

CUDA Profiler Output modes

Enumerator:

Output mode Key-Value pair format.
Output mode Comma separated values format.

enum cudaResourceType

CUDA resource types

Enumerator:

Array resource
Mipmapped array resource
Linear resource
Pitch 2D resource

enum cudaResourceViewFormat

CUDA texture resource view formats

Enumerator:

No resource view format (use underlying resource format)
1 channel unsigned 8-bit integers
2 channel unsigned 8-bit integers
4 channel unsigned 8-bit integers
1 channel signed 8-bit integers
2 channel signed 8-bit integers
4 channel signed 8-bit integers
1 channel unsigned 16-bit integers
2 channel unsigned 16-bit integers
4 channel unsigned 16-bit integers
1 channel signed 16-bit integers
2 channel signed 16-bit integers
4 channel signed 16-bit integers
1 channel unsigned 32-bit integers
2 channel unsigned 32-bit integers
4 channel unsigned 32-bit integers
1 channel signed 32-bit integers
2 channel signed 32-bit integers
4 channel signed 32-bit integers
1 channel 16-bit floating point
2 channel 16-bit floating point
4 channel 16-bit floating point
1 channel 32-bit floating point
2 channel 32-bit floating point
4 channel 32-bit floating point
Block compressed 1
Block compressed 2
Block compressed 3
Block compressed 4 unsigned
Block compressed 4 signed
Block compressed 5 unsigned
Block compressed 5 signed
Block compressed 6 unsigned half-float
Block compressed 6 signed half-float
Block compressed 7

enum cudaSharedCarveout

Shared memory carveout configurations. These may be passed to cudaFuncSetAttribute

Enumerator:

No preference for shared memory or L1 (default)
Prefer maximum available shared memory, minimum L1 cache
Prefer maximum available L1 cache, minimum shared memory

enum cudaSharedMemConfig

CUDA shared memory configuration

enum cudaStreamCaptureMode

Possible modes for stream capture thread interactions. For more details see cudaStreamBeginCapture and cudaThreadExchangeStreamCaptureMode

enum cudaStreamCaptureStatus

Possible stream capture statuses returned by cudaStreamIsCapturing

Enumerator:

Stream is not capturing
Stream is actively capturing
Stream is part of a capture sequence that has been invalidated, but not terminated

enum cudaSurfaceBoundaryMode

CUDA Surface boundary modes

Enumerator:

Zero boundary mode
Clamp boundary mode
Trap boundary mode

enum cudaSurfaceFormatMode

CUDA Surface format modes

Enumerator:

Forced format mode
Auto format mode

enum cudaTextureAddressMode

CUDA texture address modes

Enumerator:

Wrapping address mode
Clamp to edge address mode
Mirror address mode
Border address mode

enum cudaTextureFilterMode

CUDA texture filter modes

Enumerator:

Point filter mode
Linear filter mode

enum cudaTextureReadMode

CUDA texture read modes

Enumerator:

Read texture as specified element type
Read texture as normalized float

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