Provided by: nvidia-cuda-dev_10.1.243-3_amd64 
NAME
Field Value Enums -
Data Structures
struct nvmlFieldValue_t
Defines
#define NVML_FI_DEV_ECC_CURRENT 1
Current ECC mode. 1=Active. 0=Inactive.
#define NVML_FI_DEV_ECC_PENDING 2
Pending ECC mode. 1=Active. 0=Inactive.
#define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3
Total single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4
Total double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5
Total single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6
Total double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_SBE_VOL_L1 7
L1 cache single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_L1 8
L1 cache double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_VOL_L2 9
L2 cache single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_L2 10
L2 cache double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_VOL_DEV 11
Device memory single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_DEV 12
Device memory double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_VOL_REG 13
Register file single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_REG 14
Register file double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_VOL_TEX 15
Texture memory single bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_TEX 16
Texture memory double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_DBE_VOL_CBU 17
CBU double bit volatile ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_L1 18
L1 cache single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_L1 19
L1 cache double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_L2 20
L2 cache single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_L2 21
L2 cache double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_DEV 22
Device memory single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_DEV 23
Device memory double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_REG 24
Register File single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_REG 25
Register File double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_SBE_AGG_TEX 26
Texture memory single bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_TEX 27
Texture memory double bit aggregate (persistent) ECC errors.
#define NVML_FI_DEV_ECC_DBE_AGG_CBU 28
CBU double bit aggregate ECC errors.
#define NVML_FI_DEV_RETIRED_SBE 29
Number of retired pages because of single bit errors.
#define NVML_FI_DEV_RETIRED_DBE 30
Number of retired pages because of double bit errors.
#define NVML_FI_DEV_RETIRED_PENDING 31
If any pages are pending retirement. 1=yes. 0=no.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32
NVLink flow control CRC Error Counter for Lane 0.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33
NVLink flow control CRC Error Counter for Lane 1.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34
NVLink flow control CRC Error Counter for Lane 2.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35
NVLink flow control CRC Error Counter for Lane 3.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36
NVLink flow control CRC Error Counter for Lane 4.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37
NVLink flow control CRC Error Counter for Lane 5.
#define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38
NVLink flow control CRC Error Counter total for all Lanes.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39
NVLink data CRC Error Counter for Lane 0.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40
NVLink data CRC Error Counter for Lane 1.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41
NVLink data CRC Error Counter for Lane 2.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42
NVLink data CRC Error Counter for Lane 3.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43
NVLink data CRC Error Counter for Lane 4.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44
NVLink data CRC Error Counter for Lane 5.
#define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45
NvLink data CRC Error Counter total for all Lanes.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46
NVLink Replay Error Counter for Lane 0.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47
NVLink Replay Error Counter for Lane 1.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48
NVLink Replay Error Counter for Lane 2.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49
NVLink Replay Error Counter for Lane 3.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50
NVLink Replay Error Counter for Lane 4.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51
NVLink Replay Error Counter for Lane 5.
#define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52
NVLink Replay Error Counter total for all Lanes.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53
NVLink Recovery Error Counter for Lane 0.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54
NVLink Recovery Error Counter for Lane 1.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55
NVLink Recovery Error Counter for Lane 2.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56
NVLink Recovery Error Counter for Lane 3.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57
NVLink Recovery Error Counter for Lane 4.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58
NVLink Recovery Error Counter for Lane 5.
#define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59
NVLink Recovery Error Counter total for all Lanes.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60
NVLink Bandwidth Counter for Counter Set 0, Lane 0.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61
NVLink Bandwidth Counter for Counter Set 0, Lane 1.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62
NVLink Bandwidth Counter for Counter Set 0, Lane 2.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63
NVLink Bandwidth Counter for Counter Set 0, Lane 3.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64
NVLink Bandwidth Counter for Counter Set 0, Lane 4.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65
NVLink Bandwidth Counter for Counter Set 0, Lane 5.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66
NVLink Bandwidth Counter Total for Counter Set 0, All Lanes.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67
NVLink Bandwidth Counter for Counter Set 1, Lane 0.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68
NVLink Bandwidth Counter for Counter Set 1, Lane 1.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69
NVLink Bandwidth Counter for Counter Set 1, Lane 2.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70
NVLink Bandwidth Counter for Counter Set 1, Lane 3.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71
NVLink Bandwidth Counter for Counter Set 1, Lane 4.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72
NVLink Bandwidth Counter for Counter Set 1, Lane 5.
#define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73
NVLink Bandwidth Counter Total for Counter Set 1, All Lanes.
#define NVML_FI_DEV_PERF_POLICY_POWER 74
Perf Policy Counter for Power Policy.
#define NVML_FI_DEV_PERF_POLICY_THERMAL 75
Perf Policy Counter for Thermal Policy.
#define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76
Perf Policy Counter for Sync boost Policy.
#define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77
Perf Policy Counter for Board Limit.
#define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78
Perf Policy Counter for Low GPU Utilization Policy.
#define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79
Perf Policy Counter for Reliability Policy.
#define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80
Perf Policy Counter for Total App Clock Policy.
#define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81
Perf Policy Counter for Total Base Clocks Policy.
#define NVML_FI_DEV_MEMORY_TEMP 82
Memory temperature for the device.
#define NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION 83
Total energy consumption for the GPU in mJ since the driver was last reloaded.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L0 84
NVLink Speed in MBps for Link 0.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L1 85
NVLink Speed in MBps for Link 1.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L2 86
NVLink Speed in MBps for Link 2.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L3 87
NVLink Speed in MBps for Link 3.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L4 88
NVLink Speed in MBps for Link 4.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_L5 89
NVLink Speed in MBps for Link 5.
#define NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON 90
Common NVLink Speed in MBps for active links.
#define NVML_FI_DEV_NVLINK_LINK_COUNT 91
Number of NVLinks present on the device.
#define NVML_FI_DEV_RETIRED_PENDING_SBE 92
If any pages are pending retirement due to SBE. 1=yes. 0=no.
#define NVML_FI_DEV_RETIRED_PENDING_DBE 93
If any pages are pending retirement due to DBE. 1=yes. 0=no.
#define NVML_FI_DEV_PCIE_REPLAY_COUNTER 94
PCIe replay counter.
#define NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER 95
PCIe replay rollover counter.
#define NVML_FI_MAX 96
One greater than the largest field ID defined above.
Define Documentation
#define NVML_FI_DEV_ECC_CURRENT 1
Field Identifiers.
All Identifiers pertain to a device. Each ID is only used once and is guaranteed never to change.
Author
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Version 1.1 28 Jul 2019 Field Value Enums(3)