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Device Structs


#define NVML_VALUE_NOT_AVAILABLE (-1)
#define NVML_DEVICE_PCI_BUS_ID_BUFFER_SIZE 32
#define NVML_DEVICE_PCI_BUS_ID_BUFFER_V2_SIZE 16
#define NVML_DEVICE_PCI_BUS_ID_LEGACY_FMT '%04X:%02X:%02X.0'
#define NVML_DEVICE_PCI_BUS_ID_FMT '%08X:%02X:%02X.0'
#define NVML_DEVICE_PCI_BUS_ID_FMT_ARGS(pciInfo)
#define NVML_NVLINK_MAX_LINKS 6
#define NVML_MAX_PHYSICAL_BRIDGE (128)


enum nvmlBridgeChipType_t
enum nvmlNvLinkUtilizationCountUnits_t
enum nvmlNvLinkUtilizationCountPktTypes_t
enum nvmlNvLinkCapability_t
enum nvmlNvLinkErrorCounter_t
enum nvmlGpuTopologyLevel_t
enum nvmlSamplingType_t { NVML_TOTAL_POWER_SAMPLES = 0, NVML_GPU_UTILIZATION_SAMPLES = 1, NVML_MEMORY_UTILIZATION_SAMPLES = 2, NVML_ENC_UTILIZATION_SAMPLES = 3, NVML_DEC_UTILIZATION_SAMPLES = 4, NVML_PROCESSOR_CLK_SAMPLES = 5, NVML_MEMORY_CLK_SAMPLES = 6 }
enum nvmlPcieUtilCounter_t
enum nvmlValueType_t
enum nvmlPerfPolicyType_t { NVML_PERF_POLICY_POWER = 0, NVML_PERF_POLICY_THERMAL = 1, NVML_PERF_POLICY_SYNC_BOOST = 2, NVML_PERF_POLICY_BOARD_LIMIT = 3, NVML_PERF_POLICY_LOW_UTILIZATION = 4, NVML_PERF_POLICY_RELIABILITY = 5, NVML_PERF_POLICY_TOTAL_APP_CLOCKS = 10, NVML_PERF_POLICY_TOTAL_BASE_CLOCKS = 11 }

Buffer size guaranteed to be large enough for pci bus id

Buffer size guaranteed to be large enough for pci bus id for busIdLegacy

PCI format string for busId

Value:

(pciInfo)->domain,                                                     (pciInfo)->bus,                                                        (pciInfo)->device
Utility macro for filling the pci bus id format from a nvmlPciInfo_t

PCI format string for busIdLegacy

Maximum limit on Physical Bridges per Board

Maximum number of NvLink links supported

Special constant that some fields take when they are not available. Used when only part of the struct is not available.

Each structure explicitly states when to check for this value.

enum nvmlBridgeChipType_t

Enum to represent type of bridge chip

enum nvmlGpuTopologyLevel_t

Represents level relationships within a system between two GPUs The enums are spaced to allow for future relationships

enum nvmlNvLinkCapability_t

Enum to represent NvLink queryable capabilities

enum nvmlNvLinkErrorCounter_t

Enum to represent NvLink queryable error counters

enum nvmlNvLinkUtilizationCountPktTypes_t

Enum to represent the NvLink utilization counter packet types to count ** this is ONLY applicable with the units as packets or bytes ** as specified in nvmlNvLinkUtilizationCountUnits_t ** all packet filter descriptions are target GPU centric ** these can be 'OR'd' together

enum nvmlNvLinkUtilizationCountUnits_t

Enum to represent the NvLink utilization counter packet units

enum nvmlPcieUtilCounter_t

Represents the queryable PCIe utilization counters

enum nvmlPerfPolicyType_t

Represents type of perf policy for which violation times can be queried

Enumerator:

How long did power violations cause the GPU to be below application clocks.
How long did thermal violations cause the GPU to be below application clocks.
How long did sync boost cause the GPU to be below application clocks.
How long did the board limit cause the GPU to be below application clocks.
How long did low utilization cause the GPU to be below application clocks.
How long did the board reliability limit cause the GPU to be below application clocks.
Total time the GPU was held below application clocks by any limiter (0 - 5 above).
Total time the GPU was held below base clocks.

enum nvmlSamplingType_t

Represents Type of Sampling Event

Enumerator:

To represent total power drawn by GPU.
To represent percent of time during which one or more kernels was executing on the GPU.
To represent percent of time during which global (device) memory was being read or written.
To represent percent of time during which NVENC remains busy.
To represent percent of time during which NVDEC remains busy.
To represent processor clock samples.
To represent memory clock samples.

enum nvmlValueType_t

Represents the type for sample value returned

Generated automatically by Doxygen for NVML from the source code.