NAME

       vrename - change signal names across many Verilog files

SYNOPSIS

         vrename <filename_or_directory>...

DESCRIPTION

       Vrename will allow a signal to be changed across all levels of the design hierarchy, or to
       create a cross reference of signal names.  (It actually includes module names, macros, and
       other definitions, so those can be changed too.)

       Vpm uses a three step process.  First, use

           vrename --list  [<file.v>...]  [<directory>....]

       This reads the specified files, or all files below the specified directory, and creates a
       signals.vrename file.

       Now, edit the signals.vrename file manually to specify the new signal names.  Then, use

           vrename --change [<file.v>...]  [<directory>....]

       Note that in the signals.vrename file any signal names including special characters must
       follow Verilog naming rules in that they must be escaped with a leading backslash and
       trailing space.  Vrename will attempt to preserve spacing when changing escaped to non-
       escaped names and vice-versa, however in some cases extra whitespace may be inserted to
       ensure proper downstream parsing.

ARGUMENTS

       vrename takes the following arguments:

       --help
           Displays this message and program version and exits.

       --version
           Displays program version and exits.

       --change
           Take the signals file signals.vrename in the current directory and change the signals
           in the design as specified by the signals file.  Either --list or --change must be
           specified.

       --changefile {file}
           Use the given filename instead of "signals.vrename".

       --changelang
           Include in the signals.vrename file the template needed to change the language
           standard for the file.  For the first run, use "--list --changelang" and --language to
           specify the file's original language, then rerun with the "--change" option.  The
           files will get escaped identifiers for the most recent Verilog standard.  For example
           with --language 1364-2005, "do" will become "\do ".

       --crypt
           With --list, randomize the signal renames.  With --change, compress spaces and
           comments and apply those renames listed in the file (presumably created with vrename
           --list --crypt).

           The comment /*ENCRYPT_ME*/ must be included in all files that need to be encrypted, or
           use the --cryptall flag.  If a signal should not be encrypted, it can simply be set in
           the signals.vrename list to be changed to itself.  After encrypting, you may want to
           save the signals.vrename file so you have a key for decoding, and also so that it may
           be used for the next encryption run.  When used in this way for the next encryption
           run, only new signals will get new encryptions, all other encryptions will be
           encrypted the same.

       --cryptall
           As with --crypt, but put cryptic names into signals.vrename even if the file does not
           include ENCRYPT_ME.  Generally you will then need to edit the signals.vrename file
           manually to exclude any top level signals that should be preserved.

       --keywords
           Include keywords in the renaming list.  Default is to ignore keywords, as changing a
           keyword will probably result in unrunnable code, however, occasionally it may be
           necessary to rename signals which happen to match the name of keywords recently added
           to the language (such as 'bit').

       --language
       <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012|1800-2017|1800-2023>
           Set the language standard for the files.  This determines which tokens are signals
           versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop
           keyword).

       --list
           Create a list of signals in the design and write to signals.vrename.  Either --list or
           --change must be specified.

       --nowrite
           Don't write the actual changes, just report the files that would be changed.

       --o {dir}
           Use the given directory for output instead of the current directory.

       --read
           Read the changes list, allows --list to append to the changes already read.

       --xref
           Include a cross reference of where the signals are used.  --list must also be
           specified.

DISTRIBUTION

       Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool
       suite.  The latest version is available from CPAN and from
       <https://www.veripool.org/verilog-perl>.

       Copyright 2000-2024 by Wilson Snyder.  This package is free software; you can redistribute
       it and/or modify it under the terms of either the GNU Lesser General Public License
       Version 3 or the Perl Artistic License Version 2.0.

AUTHORS

       Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

       Verilog-Perl, Verilog::Parser